On Tue, Jun 17, 2008 at 01:31:03PM -0000, James Johnston wrote: > Doh... problem solved... figured it out... My minimum touching copper > overlap was 10 mils when I was running 8 mil traces. That's a new DRC > setting I'm not used to, but good to know it's there.
The PCB DRC leaves a lot to be desired. In this case it is treating a line under another copper feature as something which could "erode" when etched. -- Ben Jackson AD7GD <[EMAIL PROTECTED]> http://www.ben.com/ _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
