Eric Brombaugh wrote: > Ben Jackson wrote: Writing Verilog is at the abstraction level of approximately >> a macro assembler. At the high end it might reach up into the level of >> BASIC. > > No arguments here. OTOH, if you actually look at what's going on inside > of an HDL synthesis tool as it turns your RTL into gates, I think you'd > see that it's at least as complex as what a good optimizing C compiler > is doing.
Sure, some of the braininess encapsulated in FPGA tools is good. There's just not a rich marketplace of tool sellers and few open tools, (bitstream program format secrecy), and you have few standards so higher levels of abstraction still languish at the theoretical stage not available as pro tools. John Griessen _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
