Ben Jackson wrote:
> On Mon, May 11, 2009 at 01:52:15PM -0700, Eric Brombaugh wrote:
>> 1) A task that requires a lot of smart people to complete must suffer 
>> from a lack of adequate tools.
>>
>> 2) A task that can be completed with inadequate tools can't be very complex.
> 
> I don't know that you can decompose my position like that.  A task that
> requires a lot of smart people to complete would take fewer people if
> the tools were better.

.
.
.
.
> I would compare the current state of FPGA development tools with my early
> 8-bit computer experience.  On my Commodore 64 I cared about every memory
> location on the system.  I wrote anything remotely important by hand in
> assembly.  Writing Verilog is at the abstraction level of approximately
> a macro assembler.  At the high end it might reach up into the level of
> BASIC.

Al's remarks under subject "C++ HDL" are what I think is the reason for this gap
in HW design vs SW design ability even after plenty of time.  The gist of it 
is, university education
supports proprietary tools in HW and SW design.

I would add the way chip design companies rely so much on 3 vendors for all 
design tools
reduces the creative options of engineers so they don't have much chance to 
evolve tools
further -- the secrecy of proprietary tool work flows stops that.  The price 
tags on chip SW
are enough to get lawyers involved in any borrowing of licensed tools and call 
it theft and cut it off.
The chip Co's business is chip production flow, so they don't allow such 
development on their time.

The proverbial "cad guy" at a chip company evolves to quit and work for Cadence 
-- I've seen that with a  good one
that was developing tools -- they bought him out easily.   No chance to do his 
own little Co. or free publish his stuff.

How has SW design gotten farther?  Probably it's just that the development of 
tools is so close to the development
of apps for sale is all I can think of.

John Griessen

-- 
Ecosensory   Austin TX


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