John Griessen wrote: > Eric Brombaugh wrote: >> Ben Jackson wrote: > Writing Verilog is at the abstraction level of approximately >>> a macro assembler. At the high end it might reach up into the level of >>> BASIC. >> No arguments here. OTOH, if you actually look at what's going on inside >> of an HDL synthesis tool as it turns your RTL into gates, I think you'd >> see that it's at least as complex as what a good optimizing C compiler >> is doing. >
OK, I've been a CPU designer (at Intel, among other places) and also worked in the EDA industry as a s/w developer (logic and fault simulation, for the most part). And I've also been involved in C/C++ compiler development (not working on the optimizer, but trying to break it :) My perspective... HDL synthesis to silicon is way harder than compiling C++. At least an order of magnitude. There are fewer constraints, infinitely many back-end processes, and layer upon layer of NP-complete problems. Place and route interacts with timing analysis which interacts with device sizing, etc, etc... And don't forget that a couple of percent in clock speed is *huge* in profitability, so it's worth polishing the design. You get a lot more for the parts that test into the "fast" speed bin, even though it didn't cost more to make them. -dave _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
