"Johnny Rosenberg" <[email protected]> writes: >> No. That's the wrong conclusion. >> > > Well, we'll see what will happen. I am still not 100% sure how to > create symbols in the first place, so I guess things will move very > slowly to begin with…
Maybe your time is better invested by using a small FPGA for whatever you want to build, and learn Verilog to express the logic. Depends how much fun can have from learning such stuff. A deadline does not seem to be your problem. (It should be possible to draw a gschem schematic, export a verilog netlist and upload that to the FPGA too, for parts of the circuit you feel more comfortable, but then you'd need to do both, symbols and Verilog :-) -- Stephan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
