On 9/26/05, Evan Lavelle <[EMAIL PROTECTED]> wrote: > https://sourceforge.net/projects/veriwell/ > http://www.deepchip.com/items/0447-11.html
What we need isn't a Verilog simulator, what we need is a VHDL simulator, and maybe even some means of using both Verilog and VHDL together in a single design. It has always baffled me how Verilog simulators seem to be literally everywhere, but if OpenCores is any indication, ALL the truely interesting designs are VHDL. -- Samuel A. Falvo II
