Hello Karel. Am 27.09.2005 10:08:45 schrieb(en) Karel Kulhavy:
> What is better, Verilog or VHDL? There's no answer. Verilog belongs more to real hardware stuff, VHDL belongs more to behavioral simulation stuff. Both HDL have it pros and cons. Doesn't we talk this week about the open weekend in Prague? Send me an invitation and I'll held a quite funny lecture about that topic out of my 8 years of experience... Regards, -- Hagen Sankowski Email: [EMAIL PROTECTED]
