There is a phrase in yiddish, goes something like: Oy-Vey!
I've done both verilog and vhdl - like them both for different reasons.
The one I like the best is probably whichever one I am currently working
with ;-)
On Tue, 27 Sep 2005 05:26:56 -0400, Evan Lavelle <[EMAIL PROTECTED]>
wrote:
Karel Kulhavy wrote:
What is better, Verilog or VHDL?
There is, as far as I know, no English word that describes this class of
question.
If there was a word, it would mean this:
"A vexatious question of which the meaning is unknowable unless the
enquirer already knows the answer; of which the answerer is likely to
have even less knowledge than the enquirer; to which the answer is
almost invariably incorrect; and of which the answer, in the unlikely
circumstance that it was actually correct, would be of no practical
value anyway."
Now, I suspect that there may be a Germanic (or Slavonic?) word that
describes all this perfectly, and which we could steal and put in the
dictionary next to schadenfreude. Over to you, Karel.
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