changeset 636adb85b6bd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=636adb85b6bd
description:
inorder: use flattenIdx for reg indexing
- also use "threadId()" instead of readTid() everywhere
- this will help support more complex ISA indexing
diffstat:
src/cpu/inorder/cpu.cc | 31 ++++++-
src/cpu/inorder/cpu.hh | 15 ++-
src/cpu/inorder/reg_dep_map.cc | 16 +++-
src/cpu/inorder/reg_dep_map.hh | 2 +-
src/cpu/inorder/resources/use_def.cc | 126 ++++++++++++++++++----------------
src/cpu/inorder/resources/use_def.hh | 1 +
src/cpu/inorder/thread_context.cc | 38 +++++++---
src/cpu/inorder/thread_context.hh | 26 +++---
src/cpu/inorder/thread_state.hh | 4 -
9 files changed, 151 insertions(+), 108 deletions(-)
diffs (truncated from 637 to 300 lines):
diff -r 2fcd223a253b -r 636adb85b6bd src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:33 2011 -0400
@@ -1095,40 +1095,59 @@
return pipelineStage[stage_num];
}
+RegIndex
+InOrderCPU::flattenRegIdx(RegIndex reg_idx, ThreadID tid)
+{
+ if (reg_idx < FP_Base_DepTag) {
+ return isa[tid].flattenIntIndex(reg_idx);
+ } else if (reg_idx < Ctrl_Base_DepTag) {
+ reg_idx -= FP_Base_DepTag;
+ return isa[tid].flattenFloatIndex(reg_idx);
+ } else {
+ return reg_idx -= TheISA::Ctrl_Base_DepTag;
+ }
+}
+
uint64_t
-InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
+InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
{
+ DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
+ tid, reg_idx, intRegs[tid][reg_idx]);
+
return intRegs[tid][reg_idx];
}
FloatReg
-InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
+InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
{
return floatRegs.f[tid][reg_idx];
}
FloatRegBits
-InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
+InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
{;
return floatRegs.i[tid][reg_idx];
}
void
-InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
+InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
{
+ DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
+ tid, reg_idx, val);
+
intRegs[tid][reg_idx] = val;
}
void
-InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
+InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
{
floatRegs.f[tid][reg_idx] = val;
}
void
-InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
+InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
{
floatRegs.i[tid][reg_idx] = val;
}
diff -r 2fcd223a253b -r 636adb85b6bd src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:33 2011 -0400
@@ -80,6 +80,7 @@
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscReg MiscReg;
+ typedef TheISA::RegIndex RegIndex;
//DynInstPtr TypeDefs
typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -509,17 +510,19 @@
}
/** Register file accessors */
- uint64_t readIntReg(int reg_idx, ThreadID tid);
+ uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
- FloatReg readFloatReg(int reg_idx, ThreadID tid);
+ FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
- FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
+ FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
- void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
+ void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
- void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
+ void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
- void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
+ void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
+
+ RegIndex flattenRegIdx(RegIndex reg_idx, ThreadID tid);
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
diff -r 2fcd223a253b -r 636adb85b6bd src/cpu/inorder/reg_dep_map.cc
--- a/src/cpu/inorder/reg_dep_map.cc Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/reg_dep_map.cc Sun Jun 19 21:43:33 2011 -0400
@@ -64,6 +64,7 @@
RegDepMap::setCPU(InOrderCPU *_cpu)
{
cpu = _cpu;
+
}
void
@@ -97,10 +98,12 @@
void
RegDepMap::insert(unsigned idx, DynInstPtr inst)
{
- DPRINTF(RegDepMap, "Inserting [sn:%i] onto dep. list for reg. idx %i.\n",
- inst->seqNum, idx);
+ TheISA::RegIndex flat_idx = cpu->flattenRegIdx(idx, inst->threadNumber);
- regMap[idx].push_back(inst);
+ DPRINTF(RegDepMap, "Inserting [sn:%i] onto dep. list for reg. idx %i
(%i).\n",
+ inst->seqNum, idx, flat_idx);
+
+ regMap[flat_idx].push_back(inst);
inst->setRegDepEntry();
}
@@ -171,7 +174,7 @@
}
ThePipeline::DynInstPtr
-RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst)
+RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst, unsigned clean_idx)
{
std::list<DynInstPtr>::iterator list_it = regMap[reg_idx].begin();
std::list<DynInstPtr>::iterator list_end = regMap[reg_idx].end();
@@ -184,9 +187,12 @@
forward_inst = (*list_it);
list_it++;
}
+ DPRINTF(RegDepMap, "[sn:%i] Found potential forwarding value for reg %i
(%i)"
+ " w/ [sn:%i]\n",
+ inst->seqNum, reg_idx, clean_idx, inst->seqNum);
if (forward_inst) {
- int dest_reg_idx = forward_inst->getDestIdxNum(reg_idx);
+ int dest_reg_idx = forward_inst->getDestIdxNum(clean_idx);
assert(dest_reg_idx != -1);
if (forward_inst->isExecuted() &&
diff -r 2fcd223a253b -r 636adb85b6bd src/cpu/inorder/reg_dep_map.hh
--- a/src/cpu/inorder/reg_dep_map.hh Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/reg_dep_map.hh Sun Jun 19 21:43:33 2011 -0400
@@ -82,7 +82,7 @@
/** Is the current instruction able to get a forwarded value from
* another instruction for this destination register?
*/
- DynInstPtr canForward(unsigned reg_idx, DynInstPtr inst);
+ DynInstPtr canForward(unsigned reg_idx, DynInstPtr inst, unsigned
clean_idx);
/** find an instruction to forward/bypass a value from */
DynInstPtr findBypassInst(unsigned idx);
diff -r 2fcd223a253b -r 636adb85b6bd src/cpu/inorder/resources/use_def.cc
--- a/src/cpu/inorder/resources/use_def.cc Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/resources/use_def.cc Sun Jun 19 21:43:33 2011 -0400
@@ -167,48 +167,49 @@
{
case ReadSrcReg:
{
- int reg_idx = inst->_srcRegIdx[ud_idx];
+ RegIndex reg_idx = inst->_srcRegIdx[ud_idx];
+ RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, tid);
- DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source "
- "register idx %i (reg #%i).\n",
- tid, ud_idx, reg_idx);
+ DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read
source "
+ "register idx %i (reg #%i, flat#%i).\n",
+ tid, seq_num, ud_idx, reg_idx, flat_idx);
// Ask register dependency map if it is OK to read from Arch.
// Reg. File
- if (regDepMap[tid]->canRead(reg_idx, inst)) {
+ if (regDepMap[tid]->canRead(flat_idx, inst)) {
uniqueRegMap[reg_idx] = true;
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx < FP_Base_DepTag) {
- DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i"
- "from Register File:%i.\n",
- tid,
- reg_idx,
- cpu->readIntReg(reg_idx,inst->readTid()));
+ DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Int
Reg %i"
+ " (%i) from Register File:%i.\n",
+ tid, seq_num,
+ reg_idx, flat_idx,
+ cpu->readIntReg(flat_idx,inst->readTid()));
inst->setIntSrc(ud_idx,
- cpu->readIntReg(reg_idx,
+ cpu->readIntReg(flat_idx,
inst->readTid()));
} else if (reg_idx < Ctrl_Base_DepTag) {
reg_idx -= FP_Base_DepTag;
- DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i"
- "from Register File:%x (%08f).\n",
- tid,
- reg_idx,
- cpu->readFloatRegBits(reg_idx,
+ DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading
Float Reg %i"
+ " (%i) from Register File:%x (%08f).\n",
+ tid, seq_num,
+ reg_idx, flat_idx,
+ cpu->readFloatRegBits(flat_idx,
inst->readTid()),
- cpu->readFloatReg(reg_idx,
+ cpu->readFloatReg(flat_idx,
inst->readTid()));
inst->setFloatSrc(ud_idx,
- cpu->readFloatReg(reg_idx,
+ cpu->readFloatReg(flat_idx,
inst->readTid()));
} else {
reg_idx -= Ctrl_Base_DepTag;
- DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i "
- "from Register File:%i.\n",
- tid,
- reg_idx,
+ DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading
Misc Reg %i "
+ " (%i) from Register File:%i.\n",
+ tid, seq_num,
+ reg_idx, flat_idx,
cpu->readMiscReg(reg_idx,
inst->readTid()));
inst->setIntSrc(ud_idx,
@@ -220,9 +221,9 @@
regFileReads++;
ud_req->done();
} else {
- DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read because "
+ DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Unable to read
because "
"of [sn:%i] hasnt read it's registers yet.\n",
- tid, outReadSeqNum[tid]);
+ tid, seq_num, outReadSeqNum[tid]);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for "
"[sn:%i] to write\n",
tid, outReadSeqNum[tid]);
@@ -231,8 +232,9 @@
} else {
// Look for forwarding opportunities
- DynInstPtr forward_inst = regDepMap[tid]->canForward(reg_idx,
- inst);
+ DynInstPtr forward_inst = regDepMap[tid]->canForward(flat_idx,
+ inst,
+ reg_idx);
if (forward_inst) {
@@ -242,9 +244,9 @@
if (reg_idx < FP_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
- " reg value 0x%x from "
+ " reg %i (%i), value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
- tid,
+ tid, reg_idx, flat_idx,
forward_inst->readIntResult(dest_reg_idx),
forward_inst->seqNum,
inst->seqNum, ud_idx);
@@ -253,9 +255,9 @@
readIntResult(dest_reg_idx));
} else if (reg_idx < Ctrl_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
- " reg value 0x%x from "
+ " reg %i (%i) value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
- tid,
+ tid, reg_idx, flat_idx,
forward_inst->readFloatResult(dest_reg_idx),
forward_inst->seqNum, inst->seqNum,
ud_idx);
inst->setFloatSrc(ud_idx,
@@ -263,9 +265,9 @@
readFloatResult(dest_reg_idx));
} else {
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
- " reg value 0x%x from "
+ " reg %i (%i) value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
- tid,
+ tid, reg_idx, flat_idx,
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
