changeset 95168d713bc9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=95168d713bc9
description:
inorder: add types for dependency checks
diffstat:
src/cpu/inorder/cpu.cc | 7 +-
src/cpu/inorder/cpu.hh | 5 +-
src/cpu/inorder/reg_dep_map.cc | 147 +++++++++------------
src/cpu/inorder/reg_dep_map.hh | 48 +++---
src/cpu/inorder/resources/use_def.cc | 245 ++++++++++++++--------------------
src/cpu/inorder/resources/use_def.hh | 16 +-
6 files changed, 204 insertions(+), 264 deletions(-)
diffs (truncated from 858 to 300 lines):
diff -r 636adb85b6bd -r 95168d713bc9 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/cpu.cc Sun Jun 19 21:43:33 2011 -0400
@@ -1096,15 +1096,18 @@
}
RegIndex
-InOrderCPU::flattenRegIdx(RegIndex reg_idx, ThreadID tid)
+InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid)
{
if (reg_idx < FP_Base_DepTag) {
+ reg_type = IntType;
return isa[tid].flattenIntIndex(reg_idx);
} else if (reg_idx < Ctrl_Base_DepTag) {
+ reg_type = FloatType;
reg_idx -= FP_Base_DepTag;
return isa[tid].flattenFloatIndex(reg_idx);
} else {
- return reg_idx -= TheISA::Ctrl_Base_DepTag;
+ reg_type = MiscType;
+ return reg_idx - TheISA::Ctrl_Base_DepTag;
}
}
diff -r 636adb85b6bd -r 95168d713bc9 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/cpu.hh Sun Jun 19 21:43:33 2011 -0400
@@ -288,6 +288,9 @@
/** Dependency Tracker for Integer & Floating Point Regs */
RegDepMap archRegDepMap[ThePipeline::MaxThreads];
+ /** Register Types Used in Dependency Tracking */
+ enum RegType { IntType, FloatType, MiscType, NumRegTypes};
+
/** Global communication structure */
TimeBuffer<TimeStruct> timeBuffer;
@@ -522,7 +525,7 @@
void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
- RegIndex flattenRegIdx(RegIndex reg_idx, ThreadID tid);
+ RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid);
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
diff -r 636adb85b6bd -r 95168d713bc9 src/cpu/inorder/reg_dep_map.cc
--- a/src/cpu/inorder/reg_dep_map.cc Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/reg_dep_map.cc Sun Jun 19 21:43:33 2011 -0400
@@ -43,15 +43,15 @@
RegDepMap::RegDepMap(int size)
{
- regMap.resize(size);
+ regMap.resize(InOrderCPU::NumRegTypes);
+ regMap[InOrderCPU::IntType].resize(NumIntRegs);
+ regMap[InOrderCPU::FloatType].resize(NumFloatRegs);
+ regMap[InOrderCPU::MiscType].resize(NumMiscRegs);
}
RegDepMap::~RegDepMap()
{
- for (int i = 0; i < regMap.size(); i++) {
- regMap[i].clear();
- }
- regMap.clear();
+ clear();
}
string
@@ -60,6 +60,9 @@
return cpu->name() + ".RegDepMap";
}
+std::string RegDepMap::mapNames[InOrderCPU::NumRegTypes] =
+{"IntReg", "FloatReg", "MiscReg"};
+
void
RegDepMap::setCPU(InOrderCPU *_cpu)
{
@@ -70,6 +73,11 @@
void
RegDepMap::clear()
{
+ for (int i = 0; i < regMap.size(); i++) {
+ for (int j = 0; j < regMap[j].size(); j++)
+ regMap[i][j].clear();
+ regMap[i].clear();
+ }
regMap.clear();
}
@@ -84,26 +92,23 @@
inst->staticInst->getName(),
dest_regs);
- for (int i = 0; i < dest_regs; i++) {
- int idx = inst->destRegIdx(i);
-
- //if (inst->numFPDestRegs())
- // idx += TheISA::FP_Base_DepTag;
-
- insert(idx, inst);
- }
+ for (int i = 0; i < dest_regs; i++)
+ insert(inst->destRegIdx(i), inst);
}
void
-RegDepMap::insert(unsigned idx, DynInstPtr inst)
+RegDepMap::insert(RegIndex idx, DynInstPtr inst)
{
- TheISA::RegIndex flat_idx = cpu->flattenRegIdx(idx, inst->threadNumber);
+ InOrderCPU::RegType reg_type;
+ TheISA::RegIndex flat_idx = cpu->flattenRegIdx(idx, reg_type,
+ inst->threadNumber);
- DPRINTF(RegDepMap, "Inserting [sn:%i] onto dep. list for reg. idx %i
(%i).\n",
- inst->seqNum, idx, flat_idx);
+ DPRINTF(RegDepMap, "Inserting [sn:%i] onto %s dep. list for "
+ "reg. idx %i (%i).\n", inst->seqNum, mapNames[reg_type],
+ idx, flat_idx);
- regMap[flat_idx].push_back(inst);
+ regMap[reg_type][flat_idx].push_back(inst);
inst->setRegDepEntry();
}
@@ -116,52 +121,52 @@
inst->seqNum);
int dest_regs = inst->numDestRegs();
-
- for (int i = 0; i < dest_regs; i++) {
- int idx = inst->destRegIdx(i);
- remove(idx, inst);
- }
+ for (int i = 0; i < dest_regs; i++)
+ remove(inst->destRegIdx(i), inst);
}
}
void
-RegDepMap::remove(unsigned idx, DynInstPtr inst)
+RegDepMap::remove(RegIndex idx, DynInstPtr inst)
{
- std::list<DynInstPtr>::iterator list_it = regMap[idx].begin();
- std::list<DynInstPtr>::iterator list_end = regMap[idx].end();
+ InOrderCPU::RegType reg_type;
+ TheISA::RegIndex flat_idx = cpu->flattenRegIdx(idx, reg_type,
+ inst->threadNumber);
+
+ std::list<DynInstPtr>::iterator list_it =
regMap[reg_type][flat_idx].begin();
+ std::list<DynInstPtr>::iterator list_end =
regMap[reg_type][flat_idx].end();
while (list_it != list_end) {
if((*list_it) == inst) {
- regMap[idx].erase(list_it);
+ regMap[reg_type][flat_idx].erase(list_it);
break;
}
-
list_it++;
}
}
void
-RegDepMap::removeFront(unsigned idx, DynInstPtr inst)
+RegDepMap::removeFront(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
{
- std::list<DynInstPtr>::iterator list_it = regMap[idx].begin();
+ std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
- DPRINTF(RegDepMap, "[tid:%u]: Removing dependency entry on phys. reg."
+ DPRINTF(RegDepMap, "[tid:%u]: Removing dependency entry on reg. idx"
"%i for [sn:%i].\n", inst->readTid(), idx, inst->seqNum);
- assert(list_it != regMap[idx].end());
+ assert(list_it != regMap[reg_type][idx].end());
assert(inst == (*list_it));
- regMap[idx].erase(list_it);
+ regMap[reg_type][idx].erase(list_it);
}
bool
-RegDepMap::canRead(unsigned idx, DynInstPtr inst)
+RegDepMap::canRead(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
{
- if (regMap[idx].size() == 0)
+ if (regMap[reg_type][idx].size() == 0)
return true;
- std::list<DynInstPtr>::iterator list_it = regMap[idx].begin();
+ std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
if (inst->seqNum <= (*list_it)->seqNum) {
return true;
@@ -174,14 +179,15 @@
}
ThePipeline::DynInstPtr
-RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst, unsigned clean_idx)
+RegDepMap::canForward(uint8_t reg_type, unsigned reg_idx, DynInstPtr inst,
+ unsigned clean_idx)
{
- std::list<DynInstPtr>::iterator list_it = regMap[reg_idx].begin();
- std::list<DynInstPtr>::iterator list_end = regMap[reg_idx].end();
+ std::list<DynInstPtr>::iterator list_it =
regMap[reg_type][reg_idx].begin();
+ std::list<DynInstPtr>::iterator list_end = regMap[reg_type][reg_idx].end();
DynInstPtr forward_inst = NULL;
- // Look for first, oldest instruction
+ // Look for first/oldest instruction
while (list_it != list_end &&
(*list_it)->seqNum < inst->seqNum) {
forward_inst = (*list_it);
@@ -220,12 +226,12 @@
}
bool
-RegDepMap::canWrite(unsigned idx, DynInstPtr inst)
+RegDepMap::canWrite(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
{
- if (regMap[idx].size() == 0)
+ if (regMap[reg_type][idx].size() == 0)
return true;
- std::list<DynInstPtr>::iterator list_it = regMap[idx].begin();
+ std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
if (inst->seqNum <= (*list_it)->seqNum) {
return true;
@@ -238,52 +244,25 @@
return false;
}
-int
-RegDepMap::depSize(unsigned idx)
-{
- return regMap[idx].size();
-}
-
-ThePipeline::DynInstPtr
-RegDepMap::findBypassInst(unsigned idx)
-{
- std::list<DynInstPtr>::iterator list_it = regMap[idx].begin();
-
- if (depSize(idx) == 1)
- return NULL;
-
- list_it++;
-
- while (list_it != regMap[idx].end()) {
- if((*list_it)->isExecuted()) {
- return *list_it;
- break;
- }
- }
-
- return NULL;
-}
-
void
RegDepMap::dump()
{
-
- for (int idx=0; idx < regMap.size(); idx++) {
-
- if (regMap[idx].size() > 0) {
- cprintf("Reg #%i (size:%i): ", idx, regMap[idx].size());
+ for (int reg_type = 0; reg_type < InOrderCPU::NumRegTypes; reg_type++) {
+ for (int idx=0; idx < regMap.size(); idx++) {
+ if (regMap[idx].size() > 0) {
+ cprintf("Reg #%i (size:%i): ", idx,
regMap[reg_type][idx].size());
- std::list<DynInstPtr>::iterator list_it = regMap[idx].begin();
- std::list<DynInstPtr>::iterator list_end = regMap[idx].end();
-
- while (list_it != list_end) {
- cprintf("[sn:%i] ", (*list_it)->seqNum);
+ std::list<DynInstPtr>::iterator list_it =
+ regMap[reg_type][idx].begin();
+ std::list<DynInstPtr>::iterator list_end =
+ regMap[reg_type][idx].end();
- list_it++;
- }
-
- cprintf("\n");
+ while (list_it != list_end) {
+ cprintf("[sn:%i] ", (*list_it)->seqNum);
+ list_it++;
+ }
+ cprintf("\n");
+ }
}
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
