> On 2011-06-20 14:40:14, Nathan Binkert wrote:
> > src/cpu/base_dyn_inst.hh, line 924
> > <http://reviews.m5sim.org/r/751/diff/1/?file=13033#file13033line924>
> >
> >     Does the tracing get lost?
> 
> Gabe Black wrote:
>     Yes. I'm going to add it back in in subsequent changes, but it's going to 
> look different since the CPU doesn't know what the type is or how to handle 
> endianness. It'll be displayed like a string of bytes.

The CPU doesn't know its own endianness?  That seems odd.  The ISA defines it 
and has to provide it to the CPU, right?  Displaying as a string of bytes that 
the user has to byte swap in their head would suck.


> On 2011-06-20 14:40:14, Nathan Binkert wrote:
> > src/cpu/base_dyn_inst.hh, line 918
> > <http://reviews.m5sim.org/r/751/diff/1/?file=13033#file13033line918>
> >
> >     Seems that these particular functions are fine to me.  It's the ones 
> > with the switch statements that are not useful.
> 
> Gabe Black wrote:
>     Switch statements? Which are those?
>     
>     Generally speaking, these changes are eliminating the read and write 
> functions for typed memory all together and replacing them with ones that 
> just read and write blobs of whatever size. Since these are of the former 
> type and no longer used, they're getting nuked.

I was referring to the switch statements in the other diff, though they appear 
to only be for x86.


- Nathan


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On 2011-06-20 11:44:00, Gabe Black wrote:
> 
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.m5sim.org/r/751/
> -----------------------------------------------------------
> 
> (Updated 2011-06-20 11:44:00)
> 
> 
> Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and 
> Nathan Binkert.
> 
> 
> Summary
> -------
> 
> ExecContext: Get rid of the now unused read/write templated functions.
> 
> 
> Diffs
> -----
> 
>   src/cpu/base_dyn_inst.hh f12d1cd32cc7 
>   src/cpu/exec_context.hh f12d1cd32cc7 
>   src/cpu/inorder/inorder_dyn_inst.hh f12d1cd32cc7 
>   src/cpu/inorder/inorder_dyn_inst.cc f12d1cd32cc7 
>   src/cpu/simple/atomic.hh f12d1cd32cc7 
>   src/cpu/simple/atomic.cc f12d1cd32cc7 
>   src/cpu/simple/timing.hh f12d1cd32cc7 
>   src/cpu/simple/timing.cc f12d1cd32cc7 
> 
> Diff: http://reviews.m5sim.org/r/751/diff
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Gabe
> 
>

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