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src/cpu/o3/lsq_unit.hh <http://reviews.m5sim.org/r/502/#comment1837> Where does this get freed? src/cpu/o3/lsq_unit.hh <http://reviews.m5sim.org/r/502/#comment1836> Is this you being careful or can a mem mapped ipr access actually split across two different operations? Doesn't really seem like it should need to because translation crossing a cache boundary shouldn't be an issue for a memory mapped ipr, but perhaps it's easier this way? Lastly should all this mm ipr code be in the .hh file? - Ali On 2011-07-03 03:36:00, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/502/ > ----------------------------------------------------------- > > (Updated 2011-07-03 03:36:00) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Implement memory mapped IPRs for O3. > > > Diffs > ----- > > src/cpu/o3/lsq_unit.hh 1b4b9c05ad2b > src/cpu/o3/lsq_unit_impl.hh 1b4b9c05ad2b > > Diff: http://reviews.m5sim.org/r/502/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
