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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- Mem: Fix issue with prefetches originating at non-L1 caches getting stale data Prefetch requests issued from the L2 or below wouldn't check if valid data is present higher in the system. If a prefetch into the L2 occured at the same time as writeback from a higher-level cache the dirty data could be replaced in by unmodified data in memory. Diffs ----- src/mem/cache/cache_impl.hh 82ff928182c5 Diff: http://reviews.m5sim.org/r/787/diff Testing ------- Thanks, Ali _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
