changeset 0eca041a8c06 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0eca041a8c06
description:
O3: When waiting to handle an interrupt, let everything drain out.
Before this change, the commit stage would wait until the ROB and store
queue
were empty before recognizing an interrupt. The fetch stage would stop
generating instructions at an appropriate point, so commit would then
wait
until a valid time to interrupt the instruction stream. Instructions
might be
in flight after fetch but not the in the ROB or store queue (in rename,
for
instance), so this change makes commit wait until all in flight
instructions
are finished.
diffstat:
src/cpu/o3/commit_impl.hh | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diffs (16 lines):
diff -r 1ad244a20877 -r 0eca041a8c06 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Mon Aug 08 10:50:13 2011 -0500
+++ b/src/cpu/o3/commit_impl.hh Tue Aug 09 03:37:43 2011 -0700
@@ -714,9 +714,9 @@
return;
}
- // Wait until the ROB is empty and all stores have drained in
- // order to enter the interrupt.
- if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ // Wait until all in flight instructions are finished before enterring
+ // the interrupt.
+ if (cpu->instList.empty()) {
// Squash or record that I need to squash this cycle if
// an interrupt needed to be handled.
DPRINTF(Commit, "Interrupt detected.\n");
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