changeset 0ef219f1d8ca in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=0ef219f1d8ca description: Stats: Update stats for the recent O3 interrupt change.
diffstat: tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 10 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2295 ++++----- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini | 12 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 10 +- tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1080 ++-- tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout | 6 +- tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 976 ++-- 8 files changed, 2197 insertions(+), 2204 deletions(-) diffs (truncated from 5304 to 300 lines): diff -r 0eca041a8c06 -r 0ef219f1d8ca tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini Tue Aug 09 03:37:43 2011 -0700 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini Tue Aug 09 03:37:45 2011 -0700 @@ -10,13 +10,13 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem -pal=/chips/pd/randd/dist/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -931,7 +931,7 @@ [system.disk0.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -951,7 +951,7 @@ [system.disk2.image.child] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1080,7 +1080,7 @@ [system.simple_disk.disk] type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff -r 0eca041a8c06 -r 0ef219f1d8ca tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Tue Aug 09 03:37:43 2011 -0700 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Tue Aug 09 03:37:45 2011 -0700 @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 8 2011 15:02:59 -gem5 started Jul 8 2011 18:23:45 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 9 2011 03:11:31 +gem5 started Aug 9 2011 03:11:36 +gem5 executing on burrito command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 107915000 -Exiting @ tick 1898652239500 because m5_exit instruction encountered +Exiting @ tick 1897528709500 because m5_exit instruction encountered diff -r 0eca041a8c06 -r 0ef219f1d8ca tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Tue Aug 09 03:37:43 2011 -0700 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Tue Aug 09 03:37:45 2011 -0700 @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.898652 # Number of seconds simulated -sim_ticks 1898652239500 # Number of ticks simulated +sim_seconds 1.897529 # Number of seconds simulated +sim_ticks 1897528709500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56630 # Simulator instruction rate (inst/s) -host_tick_rate 1915374267 # Simulator tick rate (ticks/s) -host_mem_usage 336120 # Number of bytes of host memory used -host_seconds 991.27 # Real time elapsed on the host -sim_insts 56136028 # Number of instructions simulated -system.l2c.replacements 398212 # number of replacements -system.l2c.tagsinuse 35264.339871 # Cycle average of tags in use -system.l2c.total_refs 2531779 # Total number of references to valid blocks. -system.l2c.sampled_refs 433064 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.846201 # Average number of references to valid blocks. +host_inst_rate 133002 # Simulator instruction rate (inst/s) +host_tick_rate 4420145385 # Simulator tick rate (ticks/s) +host_mem_usage 318652 # Number of bytes of host memory used +host_seconds 429.29 # Real time elapsed on the host +sim_insts 57096369 # Number of instructions simulated +system.l2c.replacements 396849 # number of replacements +system.l2c.tagsinuse 35842.640466 # Cycle average of tags in use +system.l2c.total_refs 2454377 # Total number of references to valid blocks. +system.l2c.sampled_refs 435040 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.641727 # 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number of overall (read+write) accesses +system.l2c.demand_accesses::total 2459489 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2012636 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 446853 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2517774 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.233857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.009023 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.956345 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.850153 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.623656 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.762590 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.491860 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.191920 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.270336 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.027616 # miss rate for demand accesses +system.l2c.overall_accesses::total 2459489 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.172543 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.013595 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.946604 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.792513 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.941011 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.959497 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.464700 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.227667 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.208177 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.038151 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.270336 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.027616 # miss rate for overall accesses +system.l2c.overall_miss_rate::0 0.208177 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.038151 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 53414.390781 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1958423.806052 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::0 52974.958184 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3003457.512086 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 2301.934236 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 10702.338129 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 6821.313816 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12892.375169 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 17172.413793 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 9396.226415 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 4610.447761 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 4496.360990 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 62387.108968 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 329179.020449 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 57821.534078 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 565209.211654 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 55722.638123 # average overall miss latency _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
