Go ahead and take care of it, and I'll throw away my change that gets rid of the assert. Thanks!
Gabe On 08/14/11 22:21, Korey Sewell wrote: > Just to be clear, do you want me to update this change or are you > incorporating it into a future change? > > On Mon, Aug 15, 2011 at 1:15 AM, Gabe Black <[email protected]> wrote: > >> On 08/14/11 21:56, Korey Sewell wrote: >>> On Mon, Aug 15, 2011 at 12:48 AM, Gabe Black <[email protected]> >> wrote: >>>> The skid buffer doesn't really have anything to do with it. Instructions >>>> are on the wire from fetch when the squash comes. Because they aren't >>>> actually in one stage or another they keep coming. By the time they >>>> arrive, decode isn't processing any more instructions since it's waiting >>>> for the squash to finish. >>> Which is why you should always sort the incoming instructions before you >>> actually process them, no? That sort, will either block them (putting >> them >>> in the skidBuffer) or let them be, right? >>> >> I don't know. As I said, I didn't have time to dig around in decode to >> figure it out. If that's what we should do then go ahead. >> >> Gabe >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
