changeset ef35ce2bd73f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ef35ce2bd73f
description:
LSQ: Set store predictor to periodically clear itself as recommended in
the storesets paper.
This patch improves performance by as much as 10% on some spec
benchmarks.
diffstat:
src/cpu/o3/O3CPU.py | 2 ++
src/cpu/o3/mem_dep_unit_impl.hh | 9 ++++++---
src/cpu/o3/store_set.cc | 25 ++++++++++++++++++++++---
src/cpu/o3/store_set.hh | 18 ++++++++++++++++--
4 files changed, 46 insertions(+), 8 deletions(-)
diffs (165 lines):
diff -r 9c87727099ce -r ef35ce2bd73f src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Fri Aug 19 15:08:07 2011 -0500
+++ b/src/cpu/o3/O3CPU.py Fri Aug 19 15:08:07 2011 -0500
@@ -121,6 +121,8 @@
LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr
before check")
LSQCheckLoads = Param.Bool(True,
"Should dependency violations be checked for loads & stores or just
stores")
+ store_set_clear_period = Param.Unsigned(250000,
+ "Number of load/store insts before the dep predictor should be
invalidated")
LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
SSITSize = Param.Unsigned(1024, "Store set ID table size")
diff -r 9c87727099ce -r ef35ce2bd73f src/cpu/o3/mem_dep_unit_impl.hh
--- a/src/cpu/o3/mem_dep_unit_impl.hh Fri Aug 19 15:08:07 2011 -0500
+++ b/src/cpu/o3/mem_dep_unit_impl.hh Fri Aug 19 15:08:07 2011 -0500
@@ -45,8 +45,10 @@
template <class MemDepPred, class Impl>
MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
: _name(params->name + ".memdepunit"),
- depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
- loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
+ depPred(params->store_set_clear_period, params->SSITSize,
+ params->LFSTSize),
+ loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
+ storeBarrierSN(0), iqPtr(NULL)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
}
@@ -85,7 +87,8 @@
_name = csprintf("%s.memDep%d", params->name, tid);
id = tid;
- depPred.init(params->SSITSize, params->LFSTSize);
+ depPred.init(params->store_set_clear_period, params->SSITSize,
+ params->LFSTSize);
}
template <class MemDepPred, class Impl>
diff -r 9c87727099ce -r ef35ce2bd73f src/cpu/o3/store_set.cc
--- a/src/cpu/o3/store_set.cc Fri Aug 19 15:08:07 2011 -0500
+++ b/src/cpu/o3/store_set.cc Fri Aug 19 15:08:07 2011 -0500
@@ -34,8 +34,8 @@
#include "cpu/o3/store_set.hh"
#include "debug/StoreSet.hh"
-StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
- : SSITSize(_SSIT_size), LFSTSize(_LFST_size)
+StoreSet::StoreSet(uint64_t clear_period, int _SSIT_size, int _LFST_size)
+ : clearPeriod(clear_period), SSITSize(_SSIT_size), LFSTSize(_LFST_size)
{
DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
@@ -68,6 +68,8 @@
indexMask = SSITSize - 1;
offsetBits = 2;
+
+ memOpsPred = 0;
}
StoreSet::~StoreSet()
@@ -75,10 +77,11 @@
}
void
-StoreSet::init(int _SSIT_size, int _LFST_size)
+StoreSet::init(uint64_t clear_period, int _SSIT_size, int _LFST_size)
{
SSITSize = _SSIT_size;
LFSTSize = _LFST_size;
+ clearPeriod = clear_period;
DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
@@ -103,6 +106,8 @@
indexMask = SSITSize - 1;
offsetBits = 2;
+
+ memOpsPred = 0;
}
@@ -180,8 +185,21 @@
}
void
+StoreSet::checkClear()
+{
+ memOpsPred++;
+ if (memOpsPred > clearPeriod) {
+ DPRINTF(StoreSet, "Wiping predictor state beacuse %d ld/st executed\n",
+ clearPeriod);
+ memOpsPred = 0;
+ clear();
+ }
+}
+
+void
StoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
{
+ checkClear();
// Does nothing.
return;
}
@@ -193,6 +211,7 @@
int store_SSID;
+ checkClear();
assert(index < SSITSize);
if (!validSSIT[index]) {
diff -r 9c87727099ce -r ef35ce2bd73f src/cpu/o3/store_set.hh
--- a/src/cpu/o3/store_set.hh Fri Aug 19 15:08:07 2011 -0500
+++ b/src/cpu/o3/store_set.hh Fri Aug 19 15:08:07 2011 -0500
@@ -63,18 +63,24 @@
StoreSet() { };
/** Creates store set predictor with given table sizes. */
- StoreSet(int SSIT_size, int LFST_size);
+ StoreSet(uint64_t clear_period, int SSIT_size, int LFST_size);
/** Default destructor. */
~StoreSet();
/** Initializes the store set predictor with the given table sizes. */
- void init(int SSIT_size, int LFST_size);
+ void init(uint64_t clear_period, int SSIT_size, int LFST_size);
/** Records a memory ordering violation between the younger load
* and the older store. */
void violation(Addr store_PC, Addr load_PC);
+ /** Clears the store set predictor every so often so that all the
+ * entries aren't used and stores are constantly predicted as
+ * conflicting.
+ */
+ void checkClear();
+
/** Inserts a load into the store set predictor. This does nothing but
* is included in case other predictors require a similar function.
*/
@@ -130,6 +136,11 @@
typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
+ /** Number of loads/stores to process before wiping predictor so all
+ * entries don't get saturated
+ */
+ uint64_t clearPeriod;
+
/** Store Set ID Table size, in entries. */
int SSITSize;
@@ -141,6 +152,9 @@
// HACK: Hardcoded for now.
int offsetBits;
+
+ /** Number of memory operations predicted since last clear of predictor */
+ int memOpsPred;
};
#endif // __CPU_O3_STORE_SET_HH__
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