[gem5-dev] changeset in gem5: ARM: Add support for DIV/SDIV instructions.

[Ali Saidi]

changeset f9a495adafd9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f9a495adafd9
description:
        ARM: Add support for DIV/SDIV instructions.

diffstat:

 src/arch/arm/isa.cc               |   2 +-
 src/arch/arm/isa/formats/mult.isa |  10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletions(-)

diffs (32 lines):

diff -r ef35ce2bd73f -r f9a495adafd9 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc       Fri Aug 19 15:08:07 2011 -0500
+++ b/src/arch/arm/isa.cc       Fri Aug 19 15:08:07 2011 -0500
@@ -140,7 +140,7 @@
 
     // See section B4.1.84 of ARM ARM
     // All values are latest for ARMv7-A profile
-    miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
+    miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
     miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
     miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
     miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
diff -r ef35ce2bd73f -r f9a495adafd9 src/arch/arm/isa/formats/mult.isa
--- a/src/arch/arm/isa/formats/mult.isa Fri Aug 19 15:08:07 2011 -0500
+++ b/src/arch/arm/isa/formats/mult.isa Fri Aug 19 15:08:07 2011 -0500
@@ -394,6 +394,16 @@
                 }
             }
             break;
+          case 0x1:
+            if (op2 == 0 && m == 0 && ra == 0xf) {
+                return new Sdiv(machInst, rd, rn, rm);
+            }
+            break;
+          case 0x3:
+            if (op2 == 0 && m == 0 && ra == 0xf) {
+                return new Udiv(machInst, rd, rn, rm);
+            }
+            break;
           case 0x4:
             if (op2 == 0) {
                 if (m) {
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