changeset 83f728db3332 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=83f728db3332
description:
MIPS: Get rid of cruft in the fault classes.
Get rid of Fault classes left over from when this file was copied from
Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get
rid of
the old IntegerOverflowFault stub. The Integer version is what's
actually in
the manual, but the Arithmetic version had the implementation.
diffstat:
src/arch/mips/faults.cc | 39 +---------------------
src/arch/mips/faults.hh | 62 +------------------------------------
src/arch/mips/isa/decoder.isa | 6 +-
src/arch/mips/isa/formats/unimp.isa | 8 ++--
src/arch/mips/tlb.cc | 5 ++-
5 files changed, 15 insertions(+), 105 deletions(-)
diffs (276 lines):
diff -r d154cd83c353 -r 83f728db3332 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Mon Sep 19 06:17:19 2011 -0700
+++ b/src/arch/mips/faults.cc Mon Sep 19 06:17:19 2011 -0700
@@ -51,9 +51,6 @@
template <> FaultVals MipsFault<MachineCheckFault>::vals =
{ "Machine Check", 0x0401 };
-template <> FaultVals MipsFault<AlignmentFault>::vals =
- { "Alignment", 0x0301 };
-
template <> FaultVals MipsFault<ResetFault>::vals =
#if FULL_SYSTEM
{ "Reset Fault", 0xBFC00000};
@@ -79,11 +76,8 @@
template <> FaultVals MipsFault<ThreadFault>::vals =
{ "Thread Fault", 0x00F1 };
-template <> FaultVals MipsFault<ArithmeticFault>::vals =
- { "Arithmetic Overflow Exception", 0x180 };
-
-template <> FaultVals MipsFault<UnimplementedOpcodeFault>::vals =
- { "opdec", 0x0481 };
+template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
+ { "Integer Overflow Exception", 0x180 };
template <> FaultVals MipsFault<InterruptFault>::vals =
{ "interrupt", 0x0180 };
@@ -97,30 +91,9 @@
template <> FaultVals MipsFault<ItbInvalidFault>::vals =
{ "Invalid TLB Entry Exception (I-Fetch/LW)", 0x0180 };
-template <> FaultVals MipsFault<ItbPageFault>::vals =
- { "itbmiss", 0x0181 };
-
-template <> FaultVals MipsFault<ItbMissFault>::vals =
- { "itbmiss", 0x0181 };
-
-template <> FaultVals MipsFault<ItbAcvFault>::vals =
- { "iaccvio", 0x0081 };
-
template <> FaultVals MipsFault<ItbRefillFault>::vals =
{ "TLB Refill Exception (I-Fetch/LW)", 0x0180 };
-template <> FaultVals MipsFault<NDtbMissFault>::vals =
- { "dtb_miss_single", 0x0201 };
-
-template <> FaultVals MipsFault<PDtbMissFault>::vals =
- { "dtb_miss_double", 0x0281 };
-
-template <> FaultVals MipsFault<DtbPageFault>::vals =
- { "dfault", 0x0381 };
-
-template <> FaultVals MipsFault<DtbAcvFault>::vals =
- { "dfault", 0x0381 };
-
template <> FaultVals MipsFault<DtbInvalidFault>::vals =
{ "Invalid TLB Entry Exception (Store)", 0x0180 };
@@ -130,12 +103,6 @@
template <> FaultVals MipsFault<TLBModifiedFault>::vals =
{ "TLB Modified Exception", 0x0180 };
-template <> FaultVals MipsFault<FloatEnableFault>::vals =
- { "float_enable_fault", 0x0581 };
-
-template <> FaultVals MipsFault<IntegerOverflowFault>::vals =
- { "Integer Overflow Fault", 0x0501 };
-
template <> FaultVals MipsFault<DspStateDisabledFault>::vals =
{ "DSP Disabled Fault", 0x001a };
@@ -190,7 +157,7 @@
}
void
-ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
setExceptionState(tc, 0xC);
diff -r d154cd83c353 -r 83f728db3332 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh Mon Sep 19 06:17:19 2011 -0700
+++ b/src/arch/mips/faults.hh Mon Sep 19 06:17:19 2011 -0700
@@ -91,12 +91,6 @@
bool isNonMaskableInterrupt() {return true;}
};
-class AlignmentFault : public MipsFault<AlignmentFault>
-{
- public:
- bool isAlignmentFault() {return true;}
-};
-
class AddressErrorFault : public MipsFault<AddressErrorFault>
{
public:
@@ -118,37 +112,11 @@
#endif
};
-class UnimplementedOpcodeFault : public MipsFault<UnimplementedOpcodeFault> {};
-
-class TLBRefillIFetchFault : public MipsFault<TLBRefillIFetchFault>
-{
- public:
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-};
-
-class TLBInvalidIFetchFault : public MipsFault<TLBInvalidIFetchFault>
-{
- public:
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-};
-
-class NDtbMissFault : public MipsFault<NDtbMissFault> {};
-class PDtbMissFault : public MipsFault<PDtbMissFault> {};
-class DtbPageFault : public MipsFault<DtbPageFault> {};
-class DtbAcvFault : public MipsFault<DtbAcvFault> {};
-
static inline Fault genMachineCheckFault()
{
return new MachineCheckFault;
}
-static inline Fault genAlignmentFault()
-{
- return new AlignmentFault;
-}
-
class ResetFault : public MipsFault<ResetFault>
{
public:
@@ -173,20 +141,6 @@
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
-class DebugSingleStep : public MipsFault<DebugSingleStep>
-{
- public:
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-};
-
-class DebugInterrupt : public MipsFault<DebugInterrupt>
-{
- public:
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-};
-
class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
{
protected:
@@ -213,7 +167,7 @@
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
-class ArithmeticFault : public MipsFault<ArithmeticFault>
+class IntegerOverflowFault : public MipsFault<IntegerOverflowFault>
{
protected:
bool skipFaultingInstruction() {return true;}
@@ -287,15 +241,6 @@
#endif
};
-class ItbPageFault : public MipsFault<ItbPageFault>
-{
- public:
-#if FULL_SYSTEM
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
-};
-
class ItbInvalidFault : public MipsFault<ItbInvalidFault>
{
public:
@@ -347,11 +292,6 @@
#endif
};
-class FloatEnableFault : public MipsFault<FloatEnableFault> {};
-class ItbMissFault : public MipsFault<ItbMissFault> {};
-class ItbAcvFault : public MipsFault<ItbAcvFault> {};
-class IntegerOverflowFault : public MipsFault<IntegerOverflowFault> {};
-
class DspStateDisabledFault : public MipsFault<DspStateDisabledFault>
{
public:
diff -r d154cd83c353 -r 83f728db3332 src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Mon Sep 19 06:17:19 2011 -0700
+++ b/src/arch/mips/isa/decoder.isa Mon Sep 19 06:17:19 2011 -0700
@@ -214,7 +214,7 @@
Rd = result = Rs + Rt;
if (FULL_SYSTEM &&
findOverflow(32, result, Rs, Rt)) {
- fault = new ArithmeticFault();
+ fault = new IntegerOverflowFault();
}
}});
0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
@@ -223,7 +223,7 @@
Rd = result = Rs - Rt;
if (FULL_SYSTEM &&
findOverflow(32, result, Rs, ~Rt)) {
- fault = new ArithmeticFault();
+ fault = new IntegerOverflowFault();
}
}});
0x3: subu({{ Rd.sw = Rs.sw - Rt.sw; }});
@@ -327,7 +327,7 @@
Rt = result = Rs + imm;
if (FULL_SYSTEM &&
findOverflow(32, result, Rs, imm)) {
- fault = new ArithmeticFault();
+ fault = new IntegerOverflowFault();
}
}});
0x1: addiu({{ Rt.sw = Rs.sw + imm; }});
diff -r d154cd83c353 -r 83f728db3332 src/arch/mips/isa/formats/unimp.isa
--- a/src/arch/mips/isa/formats/unimp.isa Mon Sep 19 06:17:19 2011 -0700
+++ b/src/arch/mips/isa/formats/unimp.isa Mon Sep 19 06:17:19 2011 -0700
@@ -186,7 +186,7 @@
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst,
OPCODE,
inst2string(machInst));
- return new UnimplementedOpcodeFault;
+ return NoFault;
}
Fault
@@ -202,7 +202,7 @@
panic("attempt to execute unimplemented instruction '%s' "
"(inst %#08x, opcode %#x, binary:%s)",
mnemonic, machInst, OPCODE, inst2string(machInst));
- return new UnimplementedOpcodeFault;
+ return NoFault;
}
}
@@ -219,7 +219,7 @@
panic("attempt to execute unimplemented instruction '%s' "
"(inst %#08x, opcode %#x, binary:%s)",
mnemonic, machInst, OPCODE, inst2string(machInst));
- return new UnimplementedOpcodeFault;
+ return NoFault;
}
}
@@ -236,7 +236,7 @@
panic("attempt to execute unimplemented instruction '%s' "
"(inst %#08x, opcode %#x, binary:%s)",
mnemonic, machInst, OPCODE, inst2string(machInst));
- return new UnimplementedOpcodeFault;
+ return NoFault;
}
}
diff -r d154cd83c353 -r 83f728db3332 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Mon Sep 19 06:17:19 2011 -0700
+++ b/src/arch/mips/tlb.cc Mon Sep 19 06:17:19 2011 -0700
@@ -387,7 +387,10 @@
if (req->getVaddr() & (req->getSize() - 1)) {
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
req->getSize());
- return new AlignmentFault();
+ if (write)
+ return new StoreAddressErrorFault(req->getVaddr());
+ else
+ return new AddressErrorFault(req->getVaddr());
}
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
