changeset 9bdd52a2214c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9bdd52a2214c
description:
        x86: Add microop for fence
        This patch adds a new microop for memory barrier. The microop itself 
does
        nothing, but since it is marked as a memory barrier, the O3 CPU should 
flush
        all the pending loads and stores before the fence to the memory system.

diffstat:

 src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py        | 
 36 ++++++
 src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py | 
  8 +
 src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py          | 
 24 ++++
 src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py                 | 
 12 ++
 src/arch/x86/isa/insts/general_purpose/logical.py                            | 
 28 +++++
 src/arch/x86/isa/insts/general_purpose/semaphores.py                         | 
  8 +
 src/arch/x86/isa/microops/specop.isa                                         | 
 53 ++++++++++
 7 files changed, 169 insertions(+), 0 deletions(-)

diffs (truncated from 747 to 300 lines):

diff -r 78da831670e4 -r 9bdd52a2214c 
src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py     
Thu Nov 03 22:52:02 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py     
Thu Nov 03 22:52:21 2011 -0500
@@ -67,18 +67,22 @@
 def macroop ADD_LOCKED_M_I
 {
     limm t2, imm
+    mfence
     ldstl t1, seg, sib, disp
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop ADD_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
+    mfence
     ldstl t1, seg, riprel, disp
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop ADD_M_R
@@ -98,17 +102,21 @@
 
 def macroop ADD_LOCKED_M_R
 {
+    mfence
     ldstl t1, seg, sib, disp
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop ADD_LOCKED_P_R
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop ADD_R_M
@@ -168,18 +176,22 @@
 def macroop SUB_LOCKED_M_I
 {
     limm t2, imm
+    mfence
     ldstl t1, seg, sib, disp
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop SUB_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
+    mfence
     ldstl t1, seg, riprel, disp
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop SUB_M_R
@@ -199,17 +211,21 @@
 
 def macroop SUB_LOCKED_M_R
 {
+    mfence
     ldstl t1, seg, sib, disp
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop SUB_LOCKED_P_R
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop ADC_R_R
@@ -243,18 +259,22 @@
 def macroop ADC_LOCKED_M_I
 {
     limm t2, imm
+    mfence
     ldstl t1, seg, sib, disp
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop ADC_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
+    mfence
     ldstl t1, seg, riprel, disp
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop ADC_M_R
@@ -274,17 +294,21 @@
 
 def macroop ADC_LOCKED_M_R
 {
+    mfence
     ldstl t1, seg, sib, disp
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop ADC_LOCKED_P_R
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop ADC_R_M
@@ -344,18 +368,22 @@
 def macroop SBB_LOCKED_M_I
 {
     limm t2, imm
+    mfence
     ldstl t1, seg, sib, disp
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop SBB_LOCKED_P_I
 {
     rdip t7
     limm t2, imm
+    mfence
     ldstl t1, seg, riprel, disp
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop SBB_M_R
@@ -375,17 +403,21 @@
 
 def macroop SBB_LOCKED_M_R
 {
+    mfence
     ldstl t1, seg, sib, disp
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop SBB_LOCKED_P_R
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop NEG_R
@@ -410,16 +442,20 @@
 
 def macroop NEG_LOCKED_M
 {
+    mfence
     ldstl t1, seg, sib, disp
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop NEG_LOCKED_P
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
     stul t1, seg, riprel, disp
+    mfence
 };
 '''
diff -r 78da831670e4 -r 9bdd52a2214c 
src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
--- 
a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py  
    Thu Nov 03 22:52:02 2011 -0500
+++ 
b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py  
    Thu Nov 03 22:52:21 2011 -0500
@@ -58,17 +58,21 @@
 
 def macroop INC_LOCKED_M
 {
+    mfence
     ldstl t1, seg, sib, disp
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop INC_LOCKED_P
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop DEC_R
@@ -93,16 +97,20 @@
 
 def macroop DEC_LOCKED_M
 {
+    mfence
     ldstl t1, seg, sib, disp
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop DEC_LOCKED_P
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, riprel, disp
+    mfence
 };
 '''
diff -r 78da831670e4 -r 9bdd52a2214c 
src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py
--- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py       
Thu Nov 03 22:52:02 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py       
Thu Nov 03 22:52:21 2011 -0500
@@ -114,10 +114,12 @@
     limm t1, imm, dataSize=asz
     limm t4, 1
     roli t4, t4, imm
+    mfence
     ldstl t1, seg, sib, disp
     sexti t0, t1, imm, flags=(CF,)
     xor t1, t1, t4
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop BTC_LOCKED_P_I {
@@ -125,10 +127,12 @@
     limm t1, imm, dataSize=asz
     limm t4, 1
     roli t4, t4, imm
+    mfence
     ldstl t1, seg, riprel, disp
     sexti t0, t1, imm, flags=(CF,)
     xor t1, t1, t4
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop BTC_R_R {
@@ -168,10 +172,12 @@
     lea t3, flatseg, [dsz, t3, base], dataSize=asz
     limm t4, 1
     rol t4, t4, reg
+    mfence
     ldstl t1, seg, [scale, index, t3], disp
     sext t0, t1, reg, flags=(CF,)
     xor t1, t1, t4
     stul t1, seg, [scale, index, t3], disp
+    mfence
 };
 
 def macroop BTC_LOCKED_P_R {
@@ -180,10 +186,12 @@
     srai t3, t2, ldsz, dataSize=asz
     limm t4, 1
     rol t4, t4, reg
+    mfence
     ldstl t1, seg, [dsz, t3, t7], disp
     sext t0, t1, reg, flags=(CF,)
     xor t1, t1, t4
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