[gem5-dev] changeset in gem5: MESI Protocol: Add functions for profiling mi...

[Nilay Vaish]

changeset d9c61e6f1848 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d9c61e6f1848
description:
        MESI Protocol: Add functions for profiling misses

diffstat:

 src/mem/protocol/MESI_CMP_directory-L1cache.sm |  15 +++++++++++++++
 src/mem/protocol/MESI_CMP_directory-L2cache.sm |  18 +++++++++++++++++-
 2 files changed, 32 insertions(+), 1 deletions(-)

diffs (83 lines):

diff -r 9bdd52a2214c -r d9c61e6f1848 
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm    Thu Nov 03 22:52:21 
2011 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm    Fri Nov 04 11:26:12 
2011 -0500
@@ -679,6 +679,17 @@
     mandatoryQueue_in.recycle();
   }
 
+  action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
+    peek(mandatoryQueue_in, RubyRequest) {
+        L1IcacheMemory.profileMiss(in_msg);
+    }
+  }
+
+  action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
+    peek(mandatoryQueue_in, RubyRequest) {
+        L1DcacheMemory.profileMiss(in_msg);
+    }
+  }
 
   //*****************************************************
   // TRANSITIONS
@@ -698,6 +709,7 @@
     oo_allocateL1DCacheBlock;
     i_allocateTBE;
     a_issueGETS;
+    uu_profileDataMiss;
     k_popMandatoryQueue;
   }
 
@@ -705,6 +717,7 @@
     pp_allocateL1ICacheBlock;
     i_allocateTBE;
     ai_issueGETINSTR;
+    uu_profileInstMiss;
     k_popMandatoryQueue;
   }
 
@@ -712,6 +725,7 @@
     oo_allocateL1DCacheBlock;
     i_allocateTBE;
     b_issueGETX;
+    uu_profileDataMiss;
     k_popMandatoryQueue;
   }
 
@@ -729,6 +743,7 @@
   transition(S, Store, SM) {
     i_allocateTBE;
     c_issueUPGRADE;
+    uu_profileDataMiss;
     k_popMandatoryQueue;
   }
 
diff -r 9bdd52a2214c -r d9c61e6f1848 
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm    Thu Nov 03 22:52:21 
2011 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm    Fri Nov 04 11:26:12 
2011 -0500
@@ -716,9 +716,25 @@
     }
   }
 
+  GenericRequestType convertToGenericType(CoherenceRequestType type) {
+    if(type == CoherenceRequestType:GETS) {
+      return GenericRequestType:GETS;
+    } else if(type == CoherenceRequestType:GETX) {
+      return GenericRequestType:GETX;
+    } else if(type == CoherenceRequestType:GET_INSTR) {
+      return GenericRequestType:GET_INSTR;
+    } else if(type == CoherenceRequestType:UPGRADE) {
+      return GenericRequestType:UPGRADE;
+    } else {
+      DPRINTF(RubySlicc, "%s\n", type);
+      error("Invalid CoherenceRequestType\n");
+    }
+  }
+
   action(uu_profileMiss, "\u", desc="Profile the demand miss") {
     peek(L1RequestIntraChipL2Network_in, RequestMsg) {
-      //profile_L2Cache_miss(convertToGenericType(in_msg.Type), 
in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, 
L1CacheMachIDToProcessorNum(in_msg.Requestor));
+      L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
+                                       in_msg.AccessMode, in_msg.Prefetch);
     }
   }
 
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