Did that patch work for you, Lisa? It would be annoying to set up my own install of an appropriate version of gcc so I'm using you as a guinea pig for the older versions. If it works for you I'll commit it.
Gabe On 10/31/11 23:23, Gabe Black wrote: > Here, give this patch a try. > > Gabe > > On 10/31/11 19:59, Gabriel Michael Black wrote: >> Oh, sorry about that. I think there were only two lines where I >> changed flags, that one and the -Wno-unused-label one. For now if you >> comment those lines out of src/SConscript I think that will get it >> working again. I'll look into adding a check. >> >> Gabe >> >> Quoting Lisa Hsu <[email protected]>: >> >>> Hey Gabe, >>> >>> So, this change actually breaks with some earlier versions of GCC. For >>> example, I'm running 4.2.0 at work (for various reasons) and it doesn't >>> understand the -Wno-unused-but-set-variable flag. I can update but for >>> backward compatibility reasons, we probably should be able to compile >>> even >>> with 4.2.0. >>> >>> Can you put in a check to not add that unless GCC understands that flag? >>> >>> Thanks, >>> Lisa >>> >>> On Mon, Oct 31, 2011 at 1:24 AM, Gabe Black <[email protected]> >>> wrote: >>> >>>> After much delay, this should straighten out the majority of problems >>>> people have been having with gcc 4.6.1. Unfortunately gcc 4.6.0 >>>> seems to >>>> have a bug that makes a warning trigger when it shouldn't, but it looks >>>> like that was fixed in 4.6.1. Thanks to Ali for tracking down a bug I'd >>>> introduced in the ARM support in the original version of this change. >>>> >>>> Gabe >>>> >>>> On 10/31/11 01:19, Gabe Black wrote: >>>>> changeset 5fb918115c07 in /z/repo/gem5 >>>>> details: http://repo.gem5.org/gem5?cmd=changeset;node=5fb918115c07 >>>>> description: >>>>> GCC: Get everything working with gcc 4.6.1. >>>>> >>>>> And by "everything" I mean all the quick regressions. >>>>> >>>>> diffstat: >>>>> >>>>> src/SConscript | 2 ++ >>>>> src/arch/alpha/ev5.cc | 7 ++----- >>>>> src/arch/alpha/isa/mem.isa | 2 +- >>>>> src/arch/arm/isa/formats/fp.isa | 18 ++++++++++-------- >>>>> src/arch/arm/isa/insts/fp.isa | 4 ++-- >>>>> src/arch/arm/isa/insts/m5ops.isa | 19 +++---------------- >>>>> src/arch/arm/isa/insts/macromem.isa | 7 ++++--- >>>>> src/arch/arm/isa/insts/neon.isa | 16 +++++++--------- >>>>> src/arch/arm/isa/templates/mem.isa | 4 ++-- >>>>> src/arch/mips/isa/decoder.isa | 8 +++----- >>>>> src/arch/mips/isa/formats/mt.isa | 22 ++++++---------------- >>>>> src/arch/mips/isa/includes.isa | 2 ++ >>>>> src/arch/mips/tlb.cc | 2 -- >>>>> src/arch/power/isa/formats/mem.isa | 2 +- >>>>> src/arch/power/tlb.cc | 2 -- >>>>> src/arch/sparc/isa/formats/mem/util.isa | 5 ++--- >>>>> src/arch/x86/isa/microops/base.isa | 3 ++- >>>>> src/base/inet.cc | 1 + >>>>> src/cpu/base.cc | 3 +-- >>>>> src/cpu/inorder/cpu.cc | 8 ++------ >>>>> src/cpu/legiontrace.cc | 2 +- >>>>> src/cpu/o3/cpu.cc | 1 - >>>>> src/cpu/o3/rename_impl.hh | 16 ++++------------ >>>>> src/mem/cache/tags/iic.cc | 2 -- >>>>> src/mem/ruby/network/orion/Clock.cc | 7 ------- >>>>> src/mem/ruby/system/PersistentTable.hh | 1 + >>>>> src/mem/ruby/system/PseudoLRUPolicy.hh | 3 --- >>>>> src/python/m5/params.py | 1 + >>>>> src/python/swig/pyobject.cc | 4 ---- >>>>> 29 files changed, 60 insertions(+), 114 deletions(-) >>>>> >>>>> diffs (truncated from 695 to 300 lines): >>>>> >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/SConscript >>>>> --- a/src/SConscript Sun Oct 30 15:57:39 2011 -0500 >>>>> +++ b/src/SConscript Mon Oct 31 01:09:44 2011 -0700 >>>>> @@ -851,6 +851,8 @@ >>>>> swig_env.Append(CCFLAGS='-Wno-uninitialized') >>>>> swig_env.Append(CCFLAGS='-Wno-sign-compare') >>>>> swig_env.Append(CCFLAGS='-Wno-parentheses') >>>>> + swig_env.Append(CCFLAGS='-Wno-unused-label') >>>>> + swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable') >>>>> >>>>> werror_env = new_env.Clone() >>>>> werror_env.Append(CCFLAGS='-Werror') >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/arch/alpha/ev5.cc >>>>> --- a/src/arch/alpha/ev5.cc Sun Oct 30 15:57:39 2011 -0500 >>>>> +++ b/src/arch/alpha/ev5.cc Mon Oct 31 01:09:44 2011 -0700 >>>>> @@ -209,8 +209,6 @@ >>>>> void >>>>> ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) >>>>> { >>>>> - uint64_t old; >>>>> - >>>>> if (tc->misspeculating()) >>>>> return; >>>>> >>>>> @@ -262,12 +260,11 @@ >>>>> >>>>> case IPR_PALtemp23: >>>>> // write entire quad w/ no side-effect >>>>> - old = ipr[idx]; >>>>> - ipr[idx] = val; >>>>> #if FULL_SYSTEM >>>>> if (tc->getKernelStats()) >>>>> - tc->getKernelStats()->context(old, val, tc); >>>>> + tc->getKernelStats()->context(ipr[idx], val, tc); >>>>> #endif >>>>> + ipr[idx] = val; >>>>> break; >>>>> >>>>> case IPR_DTB_PTE: >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/arch/alpha/isa/mem.isa >>>>> --- a/src/arch/alpha/isa/mem.isa Sun Oct 30 15:57:39 2011 -0500 >>>>> +++ b/src/arch/alpha/isa/mem.isa Mon Oct 31 01:09:44 2011 -0700 >>>>> @@ -388,7 +388,7 @@ >>>>> Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, >>>>> Trace::InstRecord *traceData) >>>> const >>>>> { >>>>> - Addr EA; >>>>> + Addr EA M5_VAR_USED; >>>>> Fault fault = NoFault; >>>>> >>>>> %(fp_enable_check)s; >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/arch/arm/isa/formats/fp.isa >>>>> --- a/src/arch/arm/isa/formats/fp.isa Sun Oct 30 15:57:39 2011 -0500 >>>>> +++ b/src/arch/arm/isa/formats/fp.isa Mon Oct 31 01:09:44 2011 -0700 >>>>> @@ -561,20 +561,22 @@ >>>>> } >>>>> } >>>>> case 0xa: >>>>> + if (q) >>>>> + return new Unknown(machInst); >>>>> if (b) { >>>>> - return decodeNeonUSThreeReg<VpminD, VpminQ>( >>>>> - q, u, size, machInst, vd, vn, vm); >>>>> + return decodeNeonUSThreeUSReg<VpminD>( >>>>> + u, size, machInst, vd, vn, vm); >>>>> } else { >>>>> - return decodeNeonUSThreeReg<VpmaxD, VpmaxQ>( >>>>> - q, u, size, machInst, vd, vn, vm); >>>>> + return decodeNeonUSThreeUSReg<VpmaxD>( >>>>> + u, size, machInst, vd, vn, vm); >>>>> } >>>>> case 0xb: >>>>> if (b) { >>>>> - if (u) { >>>>> + if (u || q) { >>>>> return new Unknown(machInst); >>>>> } else { >>>>> - return decodeNeonUThreeReg<NVpaddD, NVpaddQ>( >>>>> - q, size, machInst, vd, vn, vm); >>>>> + return decodeNeonUThreeUSReg<NVpaddD>( >>>>> + size, machInst, vd, vn, vm); >>>>> } >>>>> } else { >>>>> if (u) { >>>>> @@ -1542,7 +1544,7 @@ >>>>> else >>>>> return new NVswpD<uint64_t>(machInst, vd, vm); >>>>> case 0x1: >>>>> - return decodeNeonUTwoMiscReg<NVtrnD, NVtrnQ>( >>>>> + return decodeNeonUTwoMiscSReg<NVtrnD, NVtrnQ>( >>>>> q, size, machInst, vd, vm); >>>>> case 0x2: >>>>> return decodeNeonUTwoMiscReg<NVuzpD, NVuzpQ>( >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/arch/arm/isa/insts/fp.isa >>>>> --- a/src/arch/arm/isa/insts/fp.isa Sun Oct 30 15:57:39 2011 -0500 >>>>> +++ b/src/arch/arm/isa/insts/fp.isa Mon Oct 31 01:09:44 2011 -0700 >>>>> @@ -447,7 +447,7 @@ >>>>> exec_output = "" >>>>> >>>>> singleSimpleCode = vfpEnabledCheckCode + ''' >>>>> - FPSCR fpscr = (FPSCR) FpscrExc; >>>>> + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; >>>>> FpDest = %(op)s; >>>>> ''' >>>>> singleCode = singleSimpleCode + ''' >>>>> @@ -457,7 +457,7 @@ >>>>> "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" >>>>> singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, >>>> fpscr.rMode)" >>>>> doubleCode = vfpEnabledCheckCode + ''' >>>>> - FPSCR fpscr = (FPSCR) FpscrExc; >>>>> + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; >>>>> double dest = %(op)s; >>>>> FpDestP0_uw = dblLow(dest); >>>>> FpDestP1_uw = dblHi(dest); >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/arch/arm/isa/insts/m5ops.isa >>>>> --- a/src/arch/arm/isa/insts/m5ops.isa Sun Oct 30 15:57:39 >>>> 2011 >>>> -0500 >>>>> +++ b/src/arch/arm/isa/insts/m5ops.isa Mon Oct 31 01:09:44 >>>> 2011 >>>> -0700 >>>>> @@ -54,9 +54,7 @@ >>>>> >>>>> >>>>> armCode = ''' >>>>> -#if FULL_SYSTEM >>>>> PseudoInst::arm(xc->tcBase()); >>>>> -#endif >>>>> ''' >>>>> armIop = InstObjParams("arm", "Arm", "PredOp", >>>>> { "code": armCode, >>>>> @@ -67,9 +65,7 @@ >>>>> exec_output += PredOpExecute.subst(armIop) >>>>> >>>>> quiesceCode = ''' >>>>> -#if FULL_SYSTEM >>>>> PseudoInst::quiesce(xc->tcBase()); >>>>> -#endif >>>>> ''' >>>>> quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", >>>>> { "code": quiesceCode, >>>>> @@ -80,9 +76,7 @@ >>>>> exec_output += QuiescePredOpExecute.subst(quiesceIop) >>>>> >>>>> quiesceNsCode = ''' >>>>> -#if FULL_SYSTEM >>>>> PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); >>>>> -#endif >>>>> ''' >>>>> >>>>> quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", >>>>> @@ -94,9 +88,7 @@ >>>>> exec_output += QuiescePredOpExecute.subst(quiesceNsIop) >>>>> >>>>> quiesceCyclesCode = ''' >>>>> -#if FULL_SYSTEM >>>>> PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); >>>>> -#endif >>>>> ''' >>>>> >>>>> quiesceCyclesIop = InstObjParams("quiesceCycles", >>>> "QuiesceCycles", >>>> "PredOp", >>>>> @@ -108,11 +100,9 @@ >>>>> exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) >>>>> >>>>> quiesceTimeCode = ''' >>>>> -#if FULL_SYSTEM >>>>> uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); >>>>> R0 = bits(qt_val, 31, 0); >>>>> R1 = bits(qt_val, 63, 32); >>>>> -#endif >>>>> ''' >>>>> >>>>> quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", >>>> "PredOp", >>>>> @@ -188,9 +178,7 @@ >>>>> exec_output += PredOpExecute.subst(m5exitIop) >>>>> >>>>> loadsymbolCode = ''' >>>>> -#if FULL_SYSTEM >>>>> PseudoInst::loadsymbol(xc->tcBase()); >>>>> -#endif >>>>> ''' >>>>> >>>>> loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", >>>> "PredOp", >>>>> @@ -204,6 +192,9 @@ >>>>> initparamCode = ''' >>>>> #if FULL_SYSTEM >>>>> Rt = PseudoInst::initParam(xc->tcBase()); >>>>> +#else >>>>> + PseudoInst::panicFsOnlyPseudoInst("initparam"); >>>>> + Rt = 0; >>>>> #endif >>>>> ''' >>>>> >>>>> @@ -260,11 +251,9 @@ >>>>> exec_output += PredOpExecute.subst(m5checkpointIop) >>>>> >>>>> m5readfileCode = ''' >>>>> -#if FULL_SYSTEM >>>>> int n = 4; >>>>> uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), >>>> false); >>>>> R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), >>>> offset); >>>>> -#endif >>>>> ''' >>>>> m5readfileIop = InstObjParams("m5readfile", "M5readfile", >>>> "PredOp", >>>>> { "code": m5readfileCode, >>>>> @@ -291,9 +280,7 @@ >>>>> exec_output += PredOpExecute.subst(m5switchcpuIop) >>>>> >>>>> m5addsymbolCode = ''' >>>>> -#if FULL_SYSTEM >>>>> PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); >>>>> -#endif >>>>> ''' >>>>> m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", >>>> "PredOp", >>>>> { "code": m5addsymbolCode, >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 >>>> src/arch/arm/isa/insts/macromem.isa >>>>> --- a/src/arch/arm/isa/insts/macromem.isa Sun Oct 30 15:57:39 >>>> 2011 >>>> -0500 >>>>> +++ b/src/arch/arm/isa/insts/macromem.isa Mon Oct 31 01:09:44 >>>> 2011 >>>> -0700 >>>>> @@ -563,15 +563,16 @@ >>>>> >>>>> let {{ >>>>> exec_output = '' >>>>> - for type in ('uint8_t', 'uint16_t', 'uint32_t'): >>>>> + for typeSize in (8, 16, 32): >>>>> for sRegs in 1, 2: >>>>> - for dRegs in range(sRegs, 5): >>>>> + for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, >>>> 5)): >>>>> for format in >>>> ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop", >>>> "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop", >>>>> >>>> "MicroPackNeon%(dRegs)dto%(sRegs)dUop"): >>>>> Name = format % { "sRegs" : sRegs * 2, >>>>> "dRegs" : dRegs * 2 } >>>>> - substDict = { "class_name" : Name, "targs" : >>>> type } >>>>> + substDict = { "class_name" : Name, >>>>> + "targs" : "uint%d_t" % typeSize } >>>>> exec_output += >>>> MicroNeonExecDeclare.subst(substDict) >>>>> }}; >>>>> >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/arch/arm/isa/insts/neon.isa >>>>> --- a/src/arch/arm/isa/insts/neon.isa Sun Oct 30 15:57:39 2011 -0500 >>>>> +++ b/src/arch/arm/isa/insts/neon.isa Mon Oct 31 01:09:44 2011 -0700 >>>>> @@ -1619,10 +1619,8 @@ >>>>> threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", >>>> unsignedTypes, 2, >>>> vaddCode) >>>>> threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", >>>> unsignedTypes, 4, >>>> vaddCode) >>>>> - threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", >>>> unsignedTypes, >>>>> + threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", >>>> smallUnsignedTypes, >>>>> 2, vaddCode, pairwise=True) >>>>> - threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", >>>> unsignedTypes, >>>>> - 4, vaddCode, pairwise=True) >>>>> vaddlwCode = ''' >>>>> destElem = (BigElement)srcElem1 + (BigElement)srcElem2; >>>>> ''' >>>>> @@ -2113,11 +2111,9 @@ >>>>> ''' >>>>> threeRegLongInst("vmull", "Vmullp", "SimdMultOp", >>>> smallUnsignedTypes, vmullpCode) >>>>> - threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, >>>> vmaxCode, pairwise=True) >>>>> - threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, >>>> vmaxCode, pairwise=True) >>>>> + threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, >>>> vmaxCode, pairwise=True) >>>>> - threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, >>>> vminCode, pairwise=True) >>>>> - threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, >>>> vminCode, pairwise=True) >>>>> + threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, >>>> vminCode, pairwise=True) >>>>> vqdmulhCode = ''' >>>>> FPSCR fpscr = (FPSCR) FpscrQc; >>>>> @@ -3140,8 +3136,10 @@ >>>>> destReg.elements[i + 1] = mid; >>>>> } >>>>> ''' >>>>> - twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", >>>> unsignedTypes, 2, >>>> vtrnCode) >>>>> - twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", >>>> unsignedTypes, 4, >>>> vtrnCode) >>>>> + twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", >>>>> + smallUnsignedTypes, 2, vtrnCode) >>>>> + twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", >>>>> + smallUnsignedTypes, 4, vtrnCode) >>>>> >>>>> vuzpCode = ''' >>>>> Element mid[eCount]; >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 >>>> src/arch/arm/isa/templates/mem.isa >>>>> --- a/src/arch/arm/isa/templates/mem.isa Sun Oct 30 15:57:39 >>>> 2011 >>>> -0500 >>>>> +++ b/src/arch/arm/isa/templates/mem.isa Mon Oct 31 01:09:44 >>>> 2011 >>>> -0700 >>>>> @@ -1112,7 +1112,7 @@ >>>>> (IntRegIndex)_index) >>>>> { >>>>> %(constructor)s; >>>>> - bool conditional = false; >>>>> + bool conditional M5_VAR_USED = false; >>>>> if (!(condCode == COND_AL || condCode == COND_UC)) { >>>>> conditional = true; >>>>> for (int x = 0; x < _numDestRegs; x++) { >>>>> @@ -1166,7 +1166,7 @@ >>>>> (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) >>>>> { >>>>> %(constructor)s; >>>>> - bool conditional = false; >>>>> + bool conditional M5_VAR_USED = false; >>>>> if (!(condCode == COND_AL || condCode == COND_UC)) { >>>>> conditional = true; >>>>> for (int x = 0; x < _numDestRegs; x++) { >>>>> diff -r dd77c8d0a93e -r 5fb918115c07 src/arch/mips/isa/decoder.isa >>>>> --- a/src/arch/mips/isa/decoder.isa Sun Oct 30 15:57:39 2011 -0500 >>>>> +++ b/src/arch/mips/isa/decoder.isa Mon Oct 31 01:09:44 2011 -0700 >>>>> _______________________________________________ >>>>> gem5-dev mailing list >>>>> [email protected] >>>>> http://m5sim.org/mailman/listinfo/gem5-dev >>>> _______________________________________________ >>>> gem5-dev mailing list >>>> [email protected] >>>> http://m5sim.org/mailman/listinfo/gem5-dev >>>> >>>> >>> _______________________________________________ >>> gem5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/listinfo/gem5-dev >>> >> >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
