Hi Nilay, if the CPUs were to retry requests in an ad-hoc fashion (on their own), that could potentially saturate the link/bus bandwidth with unsatisfied requests right?
On Mon, Nov 14, 2011 at 1:25 PM, Nilay Vaish <[email protected]> wrote: > Hi > > I am try to do something with LSQ in the O3 CPU. There is function called > recvRetry(). As per the documentation in the source files and the source > code itself, it seems that the cache informs the processor side that an > earlier failed request can be retired now. Why do we need this function? > Would it not be simple to let the processor retry the request on its own? > > -- > Nilay > ______________________________**_________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/**listinfo/gem5-dev<http://m5sim.org/mailman/listinfo/gem5-dev> > -- - Korey _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
