Hey all, For macroinstructions, what exactly does the IsDelayedCommit supposed to mean and force the O3 cpu to do? I have a basic understanding that it means the macroinstruction can't be interrupted, but not sure if that is actually the correct interpretation. Can someone please clarify?
Also, when looking at some traces of the O3 cpu I see registers like r34, r35 etc. Where can I find the definition of these registers in M5 and the purpose of them in the ARMv7 ISA docs? Thanks, Geoff _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
