Looking at src/arch/arm/intregs.hh indicates that r34-r35 are micro-op registers. Are they just a scratch pad to be used by the macro-instruction, and therefore specific to M5 only and not software visible?
Geoff On Mon, Nov 28, 2011 at 11:11 AM, Ali Saidi <[email protected]> wrote: > isDelayedCommit doesn't do anything wrt to the O3 CPU (at commit). It is used > at fetch to signal that the fetching shouldn't be interrupted by an interrupt. > > It's used by the simple cpu models to say that they must execute all the > micro-ops before processing any external interrupts. > > Look at intregs.hh in src/arch/arm. They are things like shadow registers > from different modes, micro-ops registers, etc. > > Ali > > On Nov 28, 2011, at 9:08 AM, Geoffrey Blake wrote: > >> Hey all, >> >> For macroinstructions, what exactly does the IsDelayedCommit supposed >> to mean and force the O3 cpu to do? I have a basic understanding that >> it means the macroinstruction can't be interrupted, but not sure if >> that is actually the correct interpretation. Can someone please >> clarify? >> >> Also, when looking at some traces of the O3 cpu I see registers like >> r34, r35 etc. Where can I find the definition of these registers in >> M5 and the purpose of them in the ARMv7 ISA docs? >> >> Thanks, >> Geoff >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
