changeset 6f92d950e904 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6f92d950e904
description:
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the
default
L1 cache mshr targets to 20.
diffstat:
configs/common/Caches.py | 2 +-
src/cpu/o3/O3CPU.py | 4 ----
tests/configs/o3-timing-mp.py | 2 +-
tests/configs/o3-timing.py | 1 +
tests/configs/pc-o3-timing.py | 2 +-
tests/configs/realview-o3-dual.py | 2 +-
tests/configs/realview-o3.py | 2 +-
tests/configs/tsunami-o3-dual.py | 2 +-
tests/configs/tsunami-o3.py | 2 +-
9 files changed, 8 insertions(+), 11 deletions(-)
diffs (106 lines):
diff -r 64207bef62c3 -r 6f92d950e904 configs/common/Caches.py
--- a/configs/common/Caches.py Thu Dec 01 00:15:22 2011 -0800
+++ b/configs/common/Caches.py Thu Dec 01 00:15:22 2011 -0800
@@ -33,7 +33,7 @@
block_size = 64
latency = '1ns'
mshrs = 10
- tgts_per_mshr = 5
+ tgts_per_mshr = 20
is_top_level = True
class L2Cache(BaseCache):
diff -r 64207bef62c3 -r 6f92d950e904 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Thu Dec 01 00:15:22 2011 -0800
+++ b/src/cpu/o3/O3CPU.py Thu Dec 01 00:15:22 2011 -0800
@@ -146,7 +146,3 @@
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
- def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
- BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
- self.icache.tgts_per_mshr = 20
- self.dcache.tgts_per_mshr = 20
diff -r 64207bef62c3 -r 6f92d950e904 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Thu Dec 01 00:15:22 2011 -0800
+++ b/tests/configs/o3-timing-mp.py Thu Dec 01 00:15:22 2011 -0800
@@ -38,7 +38,7 @@
latency = '1ns'
block_size = 64
mshrs = 4
- tgts_per_mshr = 8
+ tgts_per_mshr = 20
is_top_level = True
# ----------------------
diff -r 64207bef62c3 -r 6f92d950e904 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Thu Dec 01 00:15:22 2011 -0800
+++ b/tests/configs/o3-timing.py Thu Dec 01 00:15:22 2011 -0800
@@ -39,6 +39,7 @@
class MyL1Cache(MyCache):
is_top_level = True
+ tgts_per_mshr = 20
cpu = DerivO3CPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
diff -r 64207bef62c3 -r 6f92d950e904 tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py Thu Dec 01 00:15:22 2011 -0800
+++ b/tests/configs/pc-o3-timing.py Thu Dec 01 00:15:22 2011 -0800
@@ -42,7 +42,7 @@
latency = '1ns'
block_size = 64
mshrs = 4
- tgts_per_mshr = 8
+ tgts_per_mshr = 20
is_top_level = True
# ----------------------
diff -r 64207bef62c3 -r 6f92d950e904 tests/configs/realview-o3-dual.py
--- a/tests/configs/realview-o3-dual.py Thu Dec 01 00:15:22 2011 -0800
+++ b/tests/configs/realview-o3-dual.py Thu Dec 01 00:15:22 2011 -0800
@@ -40,7 +40,7 @@
latency = '1ns'
block_size = 64
mshrs = 4
- tgts_per_mshr = 8
+ tgts_per_mshr = 20
is_top_level = True
# ----------------------
diff -r 64207bef62c3 -r 6f92d950e904 tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py Thu Dec 01 00:15:22 2011 -0800
+++ b/tests/configs/realview-o3.py Thu Dec 01 00:15:22 2011 -0800
@@ -40,7 +40,7 @@
latency = '1ns'
block_size = 64
mshrs = 4
- tgts_per_mshr = 8
+ tgts_per_mshr = 20
is_top_level = True
# ----------------------
diff -r 64207bef62c3 -r 6f92d950e904 tests/configs/tsunami-o3-dual.py
--- a/tests/configs/tsunami-o3-dual.py Thu Dec 01 00:15:22 2011 -0800
+++ b/tests/configs/tsunami-o3-dual.py Thu Dec 01 00:15:22 2011 -0800
@@ -40,7 +40,7 @@
latency = '1ns'
block_size = 64
mshrs = 4
- tgts_per_mshr = 8
+ tgts_per_mshr = 20
is_top_level = True
# ----------------------
diff -r 64207bef62c3 -r 6f92d950e904 tests/configs/tsunami-o3.py
--- a/tests/configs/tsunami-o3.py Thu Dec 01 00:15:22 2011 -0800
+++ b/tests/configs/tsunami-o3.py Thu Dec 01 00:15:22 2011 -0800
@@ -40,7 +40,7 @@
latency = '1ns'
block_size = 64
mshrs = 4
- tgts_per_mshr = 8
+ tgts_per_mshr = 20
is_top_level = True
# ----------------------
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