changeset 4697ba9eb1ca in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=4697ba9eb1ca
description:
imported patch ext/stats_updates.patch
diffstat:
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt |
708 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |
10 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt |
10 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |
10 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt |
9 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini |
6 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout |
12 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt |
1882 +++++----
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini |
6 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout |
12 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt |
1075 ++--
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini |
6 +-
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout |
11 +-
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt |
9 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini |
4 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt |
726 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini |
4 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt |
814 ++--
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt |
718 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt |
714 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt |
808 ++--
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout |
8 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt |
708 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simout |
10 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt |
742 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/simout |
10 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt |
648 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini |
2 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout |
8 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |
11 +-
45 files changed, 4891 insertions(+), 4904 deletions(-)
diffs (truncated from 11819 to 300 lines):
diff -r 6f92d950e904 -r 4697ba9eb1ca
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Dec 01
00:15:22 2011 -0800
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Thu Dec 01
00:15:23 2011 -0800
@@ -500,7 +500,7 @@
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 6f92d950e904 -r 4697ba9eb1ca
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Dec 01 00:15:22
2011 -0800
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Thu Dec 01 00:15:23
2011 -0800
@@ -1,11 +1,9 @@
-Redirecting stdout to
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simout
-Redirecting stderr to
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 20 2011 12:27:58
-gem5 started Aug 20 2011 12:28:18
-gem5 executing on zizzer
+gem5 compiled Nov 21 2011 16:28:02
+gem5 started Nov 22 2011 16:59:04
+gem5 executing on u200540-lin
command line: build/ARM_SE/gem5.opt -d
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -40,4 +38,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 177134936000 because target called exit()
+Exiting @ tick 177098873000 because target called exit()
diff -r 6f92d950e904 -r 4697ba9eb1ca
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Thu Dec 01
00:15:22 2011 -0800
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Thu Dec 01
00:15:23 2011 -0800
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.177135 #
Number of seconds simulated
-sim_ticks 177134936000 #
Number of ticks simulated
+sim_seconds 0.177099 #
Number of seconds simulated
+sim_ticks 177098873000 #
Number of ticks simulated
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 142557 #
Simulator instruction rate (inst/s)
-host_tick_rate 41921641 #
Simulator tick rate (ticks/s)
-host_mem_usage 216920 #
Number of bytes of host memory used
-host_seconds 4225.38 #
Real time elapsed on the host
-sim_insts 602359810 #
Number of instructions simulated
+host_inst_rate 166594 #
Simulator instruction rate (inst/s)
+host_tick_rate 48979898 #
Simulator tick rate (ticks/s)
+host_mem_usage 214636 #
Number of bytes of host memory used
+host_seconds 3615.75 #
Real time elapsed on the host
+sim_insts 602359805 #
Number of instructions simulated
system.cpu.dtb.inst_hits 0 #
ITB inst hits
system.cpu.dtb.inst_misses 0 #
ITB inst misses
system.cpu.dtb.read_hits 0 #
DTB read hits
@@ -51,141 +51,141 @@
system.cpu.itb.misses 0 #
DTB misses
system.cpu.itb.accesses 0 #
DTB accesses
system.cpu.workload.num_syscalls 48 #
Number of system calls
-system.cpu.numCycles 354269873 #
number of cpu cycles simulated
+system.cpu.numCycles 354197747 #
number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
-system.cpu.BPredUnit.lookups 91159436 #
Number of BP lookups
-system.cpu.BPredUnit.condPredicted 84245505 #
Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 4004866 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 86334569 #
Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 80046410 #
Number of BTB hits
+system.cpu.BPredUnit.lookups 91137531 #
Number of BP lookups
+system.cpu.BPredUnit.condPredicted 84224367 #
Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 4001637 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 86284566 #
Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 80014553 #
Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1704802 #
Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 1819 #
Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 76808344 #
Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 703901675 #
Number of instructions fetch has processed
-system.cpu.fetch.Branches 91159436 #
Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 81751212 #
Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 159188980 #
Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 18469359 #
Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 103024732 #
Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 1704311 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 1605 #
Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 76786839 #
Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 703787736 #
Number of instructions fetch has processed
+system.cpu.fetch.Branches 91137531 #
Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 81718864 #
Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 159146597 #
Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 18455506 #
Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 103039518 #
Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 28 #
Number of cycles fetch has spent waiting on interrupts, or bad addresses, or
out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 658 #
Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 74435954 #
Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1343690 #
Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 353410599 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.128136 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.980644 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 620 #
Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 74412736 #
Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1337820 #
Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 353350911 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.128080 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.980798 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 194221784 54.96% 54.96% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25626631 7.25% 62.21% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 19263980 5.45% 67.66% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 24389254 6.90% 74.56% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 11789340 3.34% 77.90% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13441910 3.80% 81.70% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4603453 1.30% 83.00% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7798173 2.21% 85.21% #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52276074 14.79% 100.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 194204457 54.96% 54.96% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25620928 7.25% 62.21% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 19248235 5.45% 67.66% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 24404617 6.91% 74.57% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 11778472 3.33% 77.90% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13409998 3.80% 81.69% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4602257 1.30% 83.00% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7805373 2.21% 85.21% #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52276574 14.79% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 #
Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 353410599 #
Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.257316 #
Number of branch fetches per cycle
-system.cpu.fetch.rate 1.986908 #
Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 98916904 #
Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 83485006 #
Number of cycles decode is blocked
-system.cpu.decode.RunCycles 137131028 #
Number of cycles decode is running
-system.cpu.decode.UnblockCycles 19492362 #
Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 14385299 #
Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 6301332 #
Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 2598 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 740264204 #
Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 7138 #
Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 14385299 #
Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 111881934 #
Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9577242 #
Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 106466 #
count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 143552765 #
Number of cycles rename is running
-system.cpu.rename.UnblockCycles 73906893 #
Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 727334722 #
Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 296 #
Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 59781135 #
Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 10308783 #
Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 341 #
Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 753003460 #
Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3381092272 #
Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3381092144 #
Number of integer rename lookups
+system.cpu.fetch.rateDist::total 353350911 #
Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.257307 #
Number of branch fetches per cycle
+system.cpu.fetch.rate 1.986991 #
Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 98877750 #
Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 83515155 #
Number of cycles decode is blocked
+system.cpu.decode.RunCycles 137076269 #
Number of cycles decode is running
+system.cpu.decode.UnblockCycles 19506954 #
Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 14374783 #
Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 6301291 #
Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 2551 #
Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 740114896 #
Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 7230 #
Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 14374783 #
Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 111843103 #
Number of cycles rename is idle
+system.cpu.rename.BlockCycles 9537973 #
Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 119731 #
count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 143514381 #
Number of cycles rename is running
+system.cpu.rename.UnblockCycles 73960940 #
Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 727174418 #
Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 286 #
Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 59845789 #
Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10289393 #
Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 334 #
Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 752889395 #
Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3380302991 #
Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3380302863 #
Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 #
Number of floating rename lookups
-system.cpu.rename.CommittedMaps 627417402 #
Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 125586053 #
Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 6434 #
count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 6436 #
count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 132024310 #
count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 179771780 #
Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 82868403 #
Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 19149565 #
Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 24496609 #
Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 702530034 #
Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 7346 #
Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 663102893 #
Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 740706 #
Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 99626728 #
Number of squashed instructions iterated over during squash; mainly for
profiling
-system.cpu.iq.iqSquashedOperandsExamined 237214631 #
Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1047 #
Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 353410599 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.876296 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.734600 #
Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 627417394 #
Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 125472001 #
Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 13297 #
count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 13294 #
count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 132095966 #
count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 179744866 #
Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 82855502 #
Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 19180586 #
Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 24795671 #
Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 702443112 #
Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 9504 #
Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 663038146 #
Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 743101 #
Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 99536301 #
Number of squashed instructions iterated over during squash; mainly for
profiling
+system.cpu.iq.iqSquashedOperandsExamined 237037166 #
Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3158 #
Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 353350911 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.876430 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.733239 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00%
# Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 85472706 24.19% 24.19% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 90623075 25.64% 49.83% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 75986397 21.50% 71.33% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 42524156 12.03% 83.36% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 25503318 7.22% 90.58% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 18123112 5.13% 95.71% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7244001 2.05% 97.76% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6628954 1.88% 99.63% #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1304880 0.37% 100.00% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 85428360 24.18% 24.18% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 90441308 25.60% 49.77% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 76153703 21.55% 71.32% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 42544702 12.04% 83.36% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 25577763 7.24% 90.60% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 18033700 5.10% 95.71% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 7283699 2.06% 97.77% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 6627828 1.88% 99.64% #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1259848 0.36% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 #
Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 #
Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 353410599 #
Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 353350911 #
Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 202122 4.87% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.87% #
attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2984901 71.87% 76.73% #
attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 966402 23.27% 100.00% #
attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 202982 4.88% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% #
attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% #
attempts to use FU when none available
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