There is no diff attached. You should really just post a review at http://reviews.gem5.org
That said, I can give a quick comment before you submit the diff. This mask must be there for ISAs that require aligned instructions but use the extra bits to encode other information. Alpha certainly does this, I'm not sure if any others do, but the masking doesn't hurt on those ISAs. The right way to create this diff is to add a const variable to each ISA's isa_traits.hh that has the mask. Something like the following for Alpha: const Addr InstructionMask = ~ULL(0x3); Then in the breakpoint code do this: Addr pc = tc->instAddr() & TheISA::InstructionMask; Gabe, when this gets posted, can you make sure that he got all of the masks right? I think you're the ISA expert in the group and are the most likely to know the rules. Nate On Mon, Dec 19, 2011 at 2:38 AM, Anders Handler <[email protected]> wrote: > Hi, > > I need some breakpoints on X86 to work thus the line > Addr pc = tc->instAddr() & ~0x3; > does not work on X86 since RIP is not always aligned. > > The diff is attached. If you agree to the change please add it to the main > repo. > > Best regards > Anders > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
