Your description is partially correct. What's supposed to happen is
that the instAddr function returns what the actual address is that an
instruction should be fetched from and that the architectural PC with
magic bits and whatnot is maintained in an ISA specific way and
retrieved with other functions. The ISA specific way is very simple
and common between all the ISAs for the most part, but there's no
requirement that it is.
This *almost* works out nicely, but there was a spot in O3 where it
was just too hard to remove the idea of pal mode at that time and I
had to make Alpha return the PAL mode bits from instAddr. Alpha is the
only ISA that does this sort of thing, and it should be fixed. There
was some email discussion about it at the time, but I don't remember
exactly what the conclusion was.
So to fix this problem, you should add an #if THE_ISA == ALPHA_ISA or
an inline check like this:
http://repo.gem5.org/gem5/file/ca98021c3f96/src/cpu/o3/fetch.hh#l332
Gabe
Quoting nathan binkert <[email protected]>:
There is no diff attached. You should really just post a review at
http://reviews.gem5.org
That said, I can give a quick comment before you submit the diff.
This mask must be there for ISAs that require aligned instructions but
use the extra bits to encode other information. Alpha certainly does
this, I'm not sure if any others do, but the masking doesn't hurt on
those ISAs. The right way to create this diff is to add a const
variable to each ISA's isa_traits.hh that has the mask. Something
like the following for Alpha:
const Addr InstructionMask = ~ULL(0x3);
Then in the breakpoint code do this:
Addr pc = tc->instAddr() & TheISA::InstructionMask;
Gabe, when this gets posted, can you make sure that he got all of the
masks right? I think you're the ISA expert in the group and are the
most likely to know the rules.
Nate
On Mon, Dec 19, 2011 at 2:38 AM, Anders Handler
<[email protected]> wrote:
Hi,
I need some breakpoints on X86 to work thus the line
Addr pc = tc->instAddr() & ~0x3;
does not work on X86 since RIP is not always aligned.
The diff is attached. If you agree to the change please add it to the main
repo.
Best regards
Anders
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