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src/cpu/base.hh <http://reviews.m5sim.org/r/944/#comment2336> At the moment there is no need to do anything for any of the CPU models when receiving a status change (they simply have no choice when it comes to address ranges anyhow). They should also never receive any functional accesses since they are master ports (and functional requests return without any backwards path). When we eventually add a snooping port for the LSQ (for ARM but potentially also others) that port will behave in a different way. - Andreas On 2011-12-23 01:00:44, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/944/ > ----------------------------------------------------------- > > (Updated 2011-12-23 01:00:44) > > > Review request for Default. > > > Summary > ------- > > CPU: Moving towards a more general port across CPU models > > This patch performs minimal changes to move the instruction and data > ports from specialised subclasses to the base CPU (to the largest > degree possible). Ultimately it servers to make the CPU(s) have a > well-defined interface to the memory sub-system. > > > Diffs > ----- > > src/cpu/BaseCPU.py ca98021c3f96 > src/cpu/base.hh ca98021c3f96 > src/cpu/base.cc ca98021c3f96 > src/cpu/inorder/InOrderCPU.py ca98021c3f96 > src/cpu/o3/O3CPU.py ca98021c3f96 > src/cpu/o3/cpu.hh ca98021c3f96 > src/cpu/o3/cpu.cc ca98021c3f96 > src/cpu/o3/fetch.hh ca98021c3f96 > src/cpu/o3/fetch_impl.hh ca98021c3f96 > src/cpu/o3/iew.hh ca98021c3f96 > src/cpu/o3/lsq.hh ca98021c3f96 > src/cpu/o3/lsq_impl.hh ca98021c3f96 > src/cpu/simple/AtomicSimpleCPU.py ca98021c3f96 > src/cpu/simple/TimingSimpleCPU.py ca98021c3f96 > src/cpu/simple/atomic.hh ca98021c3f96 > src/cpu/simple/atomic.cc ca98021c3f96 > src/cpu/simple/timing.hh ca98021c3f96 > src/cpu/simple/timing.cc ca98021c3f96 > > Diff: http://reviews.m5sim.org/r/944/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
