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Ship it! In isolation this looks like a wash... the code is pretty similar but just moved around. I don't see anything wrong with it though. I'll take your word that it's a useful step toward better things. - Steve On 2012-01-10 09:23:23, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/944/ > ----------------------------------------------------------- > > (Updated 2012-01-10 09:23:23) > > > Review request for Default. > > > Summary > ------- > > CPU: Moving towards a more general port across CPU models > > This patch performs minimal changes to move the instruction and data > ports from specialised subclasses to the base CPU (to the largest > degree possible). Ultimately it servers to make the CPU(s) have a > well-defined interface to the memory sub-system. > > > Diffs > ----- > > src/cpu/BaseCPU.py a1d5a0e2e970 > src/cpu/base.hh a1d5a0e2e970 > src/cpu/base.cc a1d5a0e2e970 > src/cpu/inorder/InOrderCPU.py a1d5a0e2e970 > src/cpu/o3/O3CPU.py a1d5a0e2e970 > src/cpu/o3/cpu.hh a1d5a0e2e970 > src/cpu/o3/cpu.cc a1d5a0e2e970 > src/cpu/o3/fetch.hh a1d5a0e2e970 > src/cpu/o3/fetch_impl.hh a1d5a0e2e970 > src/cpu/o3/iew.hh a1d5a0e2e970 > src/cpu/o3/lsq.hh a1d5a0e2e970 > src/cpu/o3/lsq_impl.hh a1d5a0e2e970 > src/cpu/simple/AtomicSimpleCPU.py a1d5a0e2e970 > src/cpu/simple/TimingSimpleCPU.py a1d5a0e2e970 > src/cpu/simple/atomic.hh a1d5a0e2e970 > src/cpu/simple/atomic.cc a1d5a0e2e970 > src/cpu/simple/timing.hh a1d5a0e2e970 > src/cpu/simple/timing.cc a1d5a0e2e970 > > Diff: http://reviews.m5sim.org/r/944/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
