> On 2012-01-04 20:32:28, Steve Reinhardt wrote: > > Looks great. I think the recvStatusChange() thing was yet another exercise > > in pointless generality, since we never found a status other than > > RangeChange. I did notice a couple of places where the comment still says > > "status change", but that's not a huge deal.
I'll try and chase those down ASAP. > On 2012-01-04 20:32:28, Steve Reinhardt wrote: > > src/mem/bus.cc, line 103 > > <http://reviews.m5sim.org/r/948/diff/1/?file=16541#file16541line103> > > > > Hey, that's not how we spell "neighbor" in these parts ;) It's a bit of a grey area... :) - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/948/#review1843 ----------------------------------------------------------- On 2011-12-19 06:00:04, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/948/ > ----------------------------------------------------------- > > (Updated 2011-12-19 06:00:04) > > > Review request for Default. > > > Summary > ------- > > MEM: Separate queries for snooping and address ranges > > This patch simplifies the address-range determination mechanism and > also unifies the naming across ports and devices. It further splits > the queries for determining if a port is snooping and what address > ranges it responds to (aiming towards a separation of > cache-maintenance ports and pure memory-mapped ports). Default > behaviours are such that most ports do not have to define isSnooping, > and master ports need not implement getAddrRanges. > > > Diffs > ----- > > src/arch/x86/interrupts.hh ca98021c3f96 > src/arch/x86/interrupts.cc ca98021c3f96 > src/arch/x86/pagetable_walker.hh ca98021c3f96 > src/arch/x86/pagetable_walker.cc ca98021c3f96 > src/cpu/base.hh ca98021c3f96 > src/cpu/base.cc ca98021c3f96 > src/cpu/inorder/resources/cache_unit.hh ca98021c3f96 > src/cpu/inorder/resources/cache_unit.cc ca98021c3f96 > src/cpu/o3/cpu.hh ca98021c3f96 > src/cpu/ozone/front_end.hh ca98021c3f96 > src/cpu/ozone/front_end_impl.hh ca98021c3f96 > src/cpu/ozone/lw_lsq.hh ca98021c3f96 > src/cpu/ozone/lw_lsq_impl.hh ca98021c3f96 > src/cpu/simple/atomic.cc ca98021c3f96 > src/cpu/testers/memtest/memtest.hh ca98021c3f96 > src/cpu/testers/memtest/memtest.cc ca98021c3f96 > src/cpu/testers/networktest/networktest.hh ca98021c3f96 > src/cpu/testers/networktest/networktest.cc ca98021c3f96 > src/dev/arm/gic.hh ca98021c3f96 > src/dev/arm/gic.cc ca98021c3f96 > src/dev/arm/pl111.hh ca98021c3f96 > src/dev/arm/pl111.cc ca98021c3f96 > src/dev/copy_engine.hh ca98021c3f96 > src/dev/io_device.hh ca98021c3f96 > src/dev/io_device.cc ca98021c3f96 > src/dev/pciconfigall.hh ca98021c3f96 > src/dev/pciconfigall.cc ca98021c3f96 > src/dev/pcidev.hh ca98021c3f96 > src/dev/pcidev.cc ca98021c3f96 > src/dev/sinic.cc ca98021c3f96 > src/dev/sparc/iob.hh ca98021c3f96 > src/dev/sparc/iob.cc ca98021c3f96 > src/dev/uart8250.hh ca98021c3f96 > src/dev/uart8250.cc ca98021c3f96 > src/dev/x86/i8042.hh ca98021c3f96 > src/dev/x86/i8042.cc ca98021c3f96 > src/dev/x86/i82094aa.hh ca98021c3f96 > src/dev/x86/intdev.hh ca98021c3f96 > src/dev/x86/intdev.cc ca98021c3f96 > src/kern/tru64/tru64_events.cc ca98021c3f96 > src/mem/bridge.hh ca98021c3f96 > src/mem/bridge.cc ca98021c3f96 > src/mem/bus.hh ca98021c3f96 > src/mem/bus.cc ca98021c3f96 > src/mem/cache/base.hh ca98021c3f96 > src/mem/cache/base.cc ca98021c3f96 > src/mem/cache/cache.hh ca98021c3f96 > src/mem/cache/cache_impl.hh ca98021c3f96 > src/mem/physical.hh ca98021c3f96 > src/mem/physical.cc ca98021c3f96 > src/mem/port.hh ca98021c3f96 > src/mem/ruby/system/RubyPort.cc ca98021c3f96 > src/mem/tport.hh ca98021c3f96 > src/sim/system.hh ca98021c3f96 > > Diff: http://reviews.m5sim.org/r/948/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
