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I have a few questions below. Also FYI...it appears that some of parts of patch don't apply cleanly to the main repo. src/mem/ruby/system/Sequencer.cc <http://reviews.m5sim.org/r/927/#comment2370> I like the term cooldown, but I think it is a little bit confusing in this situation. If I understand this code correctly, you're not trying to avoid data reads and writes before taking a checkpoint. Rather you don't want the hitcallbacks of Flush requests trying to modify memory. Is that correct? If so, I thought we already dealt with that problem by simply not setting the data pointer of flush packet. Maybe I'm missing something. src/mem/ruby/system/Sequencer.cc <http://reviews.m5sim.org/r/927/#comment2369> Did you mean to set this value to false? I'm not sure why it was ever set to true before, but it is unclear how this patch would impact this value. src/mem/ruby/system/Sequencer.cc <http://reviews.m5sim.org/r/927/#comment2371> Am I reading this correctly? Is this issuing the next fetch or flush request inside the previous request's callback? Is that how the patch used to work? If so, that seems very odd and would create one deep call stack. I must be missing something here. Possibly the next request is being schedule for the next cycle. If that is the case, then these functions should be renamed to something like "notifyFetchCompletion" or "notifyFlushCompletion" - Brad On 2012-01-03 16:43:40, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/927/ > ----------------------------------------------------------- > > (Updated 2012-01-03 16:43:40) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > Ruby: Resurrect Cache Warmup Capability > This patch resurrects ruby's cache warmup capability. It essentially > makes use of all the infrastructure that was added to the controllers, > memories and the cache recorder. > > > Diffs > ----- > > src/mem/ruby/buffers/MessageBuffer.cc 09b482ee9ae0 > src/mem/ruby/system/DMASequencer.hh 09b482ee9ae0 > src/mem/ruby/system/DirectoryMemory.cc 09b482ee9ae0 > src/mem/ruby/system/RubyPort.hh 09b482ee9ae0 > src/mem/ruby/system/RubyPort.cc 09b482ee9ae0 > src/mem/ruby/system/Sequencer.hh 09b482ee9ae0 > src/mem/ruby/system/Sequencer.cc 09b482ee9ae0 > src/mem/ruby/system/System.hh 09b482ee9ae0 > src/mem/ruby/system/System.cc 09b482ee9ae0 > > Diff: http://reviews.m5sim.org/r/927/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
