This also means that a checkpoint created with Memory Vector cannot be
used to bring up a system with Sparse Memory and vice-versa.
--
Nilay
On Sat, 7 Jan 2012, Nilay Vaish wrote:
Brad, I have updated the patch. There is one thing that I have not talked
about, which probably will not be clear from just reading the patch. The
warmup and cooldown happens differently in case of Sparse Memory compared to
Memory Vector, and hence there is a difference in timing for the two
memories.
Sparse Memory makes use of blocks allocated by the directory controller, so
while warming up the Sparse Memory, timing requests are issued for all the
blocks that were in the Sparse Memory at the time of cool down, followed
timing requests for all the blocks that were in the caches.
In case of Memory Vector, the memory pages are maintained independently of
the directory controller. So those pages can be recreated without requiring
to issue any timing requests. This results in the difference in timing.
One can, in theory, issue requests for all the blocks that make up the pages
of Memory Vector, but it is likely that many more requests will be issued
than necessary (not all blocks of a page may have been touched) and still
this is unlikely to match the timing obtained while warming up Sparse Memory.
--
Nilay
On Sat, 7 Jan 2012, Nilay Vaish wrote:
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/927/
-----------------------------------------------------------
(Updated 2012-01-07 05:15:42.888984)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and
Nathan Binkert.
Summary
-------
Ruby: Resurrect Cache Warmup Capability
This patch resurrects ruby's cache warmup capability. It essentially
makes use of all the infrastructure that was added to the controllers,
memories and the cache recorder.
Diffs (updated)
-----
src/mem/ruby/buffers/MessageBuffer.cc c3d878fbdaea
src/mem/ruby/system/DMASequencer.hh c3d878fbdaea
src/mem/ruby/system/DirectoryMemory.cc c3d878fbdaea
src/mem/ruby/system/RubyPort.hh c3d878fbdaea
src/mem/ruby/system/RubyPort.cc c3d878fbdaea
src/mem/ruby/system/Sequencer.hh c3d878fbdaea
src/mem/ruby/system/Sequencer.cc c3d878fbdaea
src/mem/ruby/system/System.hh c3d878fbdaea
src/mem/ruby/system/System.cc c3d878fbdaea
Diff: http://reviews.m5sim.org/r/927/diff
Testing
-------
Thanks,
Nilay
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