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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/980/
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Review request for Default.
Summary
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Hello everyone!
I'm Deyuan Guo, and I'm from Institute of Microelectronics, Tsinghua
University, Beijing, China.
Recently, my colleague, Zhengxing Li, has successfully booted a linux 3.1
kernel in gem5-stable by using MIPS_FS, and I did a merge with the newly gem5
r8682.
The changes are mainly in the following areas:
1. FSConfig.py and src/dev/mips:
We don't use Malta devices, but using the RealView/amba devices, which are
similar to the ARM_FS system. The MipsSystem.py and system.cc/hh in arch/mips/
and arch/mips/linux should be modified relevantly.
2. TLB:
Because MIPS does not distinguish between ITB and DTB, some related codes
should be modified, such as tlbwi/tlbwr, Random register, TLB::insertAt, Asid,
etc.
3. decoder.isa:
Some instructions need to be implemented, such as wait, rdhwr, etc.
4. Some other unimplement functions, such as interrupt, remote gdb, etc.
5. Linux kernel:
linux-3.1-rc4 and busybox-1.19.3 are selected. The mips cross compiler is
from CodeSourcery.
Below are some existing bugs related to MIPS_FS based on gem5 r8682 version. We
are planning to submit all of the MIPS_FS patches later, maybe after our Spring
Festival.
Moreover, we have done a MIPS64 extension in gem5. The mainly changes are ISA
definitions, register file definitions, and the register accessing interfaces
between ISA and CPU. We want to submit this together, but the problem is that
the 64-bit floating registers may be not compatible with the other ISAs in gem5.
Here a bug should be specially mentioned:
tc->pcState(this->vect(tc));
setTlbExceptionState(tc, this->code());
Change to:
Addr vect = this->vect(tc);
setTlbExceptionState(tc, this->code());
tc->pcState(vect);
If we set the pcState before setTlbExceptionState, the EPC in
setTlbExceptionState will be error.
If we set the pcState after setTlbExceptionState, the status.exl flag changed
in setTlbExceptionState will affect the value of this->vect(tc), then make
pcState error.
Therefore, we must get the value of vect() before setTlbExceptionState, and set
pcState after.
At last, Thank you for providing such a good research platform:)
-- guody
Diffs
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src/arch/mips/faults.hh 93c6317af258
src/arch/mips/faults.cc 93c6317af258
src/arch/mips/tlb.cc 93c6317af258
Diff: http://reviews.m5sim.org/r/980/diff
Testing
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$ ./m5term localhost 3456
==== m5 slave terminal: Terminal 0 ====
Linux version 3.1.0-rc4
...
Please press Enter to activate this console.
BusyBox v1.19.3 (2011-11-22 17:27:10 CST) built-in shell (ash)
Enter 'help' for a list of built-in commands.
# ls
bin dev home lib mnt root sys usr
boot etc init linuxrc proc sbin tmp var
# pwd
/
#
Thanks,
Deyuan
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