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Ship it! Sounds fine to me! - Steve On 2012-01-10 09:16:24, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/979/ > ----------------------------------------------------------- > > (Updated 2012-01-10 09:16:24) > > > Review request for Default. > > > Summary > ------- > > MEM: Differentiate functional cache accesses from CPU and memory > > This patch changes the functionalAccess member function in the cache > model such that it is aware of what port the access came from, i.e. if > it came from the CPU side or from the memory side. By adding this > information, it is possible to respect the 'forwardSnoops' flag for > snooping requests coming from the memory side and not forward > them. This fixes an outstanding issue with the IO bus getting accesses > that have no valid destination port and also cleans up future changes > to the bus model. > > > Diffs > ----- > > src/mem/cache/cache.hh a1d5a0e2e970 > src/mem/cache/cache_impl.hh a1d5a0e2e970 > > Diff: http://reviews.m5sim.org/r/979/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
