Hi Korey,
Getting InOrder to work is a priority for me (at least for the time
being), so any notes or tips you have would be very helpful. Do you have
any advice on a good place to start understanding these models?
Thanks,
Erik
On 10/01/12 17:51, Korey Sewell wrote:
Hey Erik/Ali,
I have some patches in my tree that get ARM compiling for gem5 inorder, but
I'm not actively working on the project.
I have some personal notes on what needs to be done for InOrder to support
ARM's microcode as well. The process you need to get it to work is use the
SimpeCPU as a "golden model" and compare the instruction trace when you
added the appropriate ARM features. Because microcode, predicated
instructions, and hardware page tables is already implemented in the
SimpleCPU and O3 models there is a good reference there and it will take
about 2-3 weeks I'd estimate to get it to work (1 week to learn the model,
2 to get in the features).
If you are interested in adding the support yourself, I'd definitely help
and there are at least 2 other people who've asked me about ARM-InOrder as
well that keep track on the mailing lists.
If you need something to get you going *now*, your best bet is probably to
reconfigure the O3 model to act like an InOrder model.
If no one takes up the task of adding ARM to InOrder, I'll eventually do it
myself (I want to see the InOrder model be useful to others), but currently
there are other first-order tasks on my plate.
(oh, and for ALPHA_FS there is a patch you can check out on the reviewboard
that will allow you to boot the InOrder model)
On Tue, Jan 10, 2012 at 11:39 AM, Ali Saidi<[email protected]> wrote:
Hi Erik,
No one is actively working on it (that I know of at
least), but it would be great to have. Korey got the model very close to
supporting ALPHA Fullsystem, so the two major things that would need to
be added are predicated execution and hardware table walking support.
Thanks,
Ali
On 10.01.2012 10:27, Erik Tomusk wrote:
Hello
gem5-dev,
Is anyone working on making the InOrder CPU model work
with ARM? If not,
what would need to be done to make it work? Or does
it make more sense
to just configure the O3CPU model to be more like
an in-order?
Thanks,
Erik
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