To start, I would read the gem5 tutorial at least through the CPU models section. You may not understand perfectly but it will help give you a good base on how the parts are interacting.
Next, I think there is at least a few pages of InOrder documentation on the gem5 site. Check that out too. After that, I would run the InOrderCPU model for hello world (using Alpha). Once you verify that's working, I'd run it again for only a few instructions (5? 10?) and turn on the InOrderCPUAll trace flag. To do that, look into how to use "--maxinsts" option and also the "debug-flags" option. If you can follow that trace and also find the code that handles the squashing (recovery from branch mispredict) then I'd think you are ready to start adding the features we need to support ARM. I'll check in the patch to compile ARM with InOrder soon. After you've done the above, getting things like predicated branches to work will involve looking at the SimpleCPU model, finding what flags mark a predicated branch, and then triggering the squash mechanisms correctly. But we'll cross that bridge when we get to it. If you have questions about development, email the dev-list and we''ll try to help you spin you up quickly. On Fri, Jan 13, 2012 at 5:22 AM, Erik Tomusk <[email protected]> wrote: > Hi Korey, > > Getting InOrder to work is a priority for me (at least for the time > being), so any notes or tips you have would be very helpful. Do you have > any advice on a good place to start understanding these models? > > Thanks, > Erik > > > On 10/01/12 17:51, Korey Sewell wrote: > >> Hey Erik/Ali, >> I have some patches in my tree that get ARM compiling for gem5 inorder, >> but >> I'm not actively working on the project. >> >> I have some personal notes on what needs to be done for InOrder to support >> ARM's microcode as well. The process you need to get it to work is use the >> SimpeCPU as a "golden model" and compare the instruction trace when you >> added the appropriate ARM features. Because microcode, predicated >> instructions, and hardware page tables is already implemented in the >> SimpleCPU and O3 models there is a good reference there and it will take >> about 2-3 weeks I'd estimate to get it to work (1 week to learn the model, >> 2 to get in the features). >> >> If you are interested in adding the support yourself, I'd definitely help >> and there are at least 2 other people who've asked me about ARM-InOrder as >> well that keep track on the mailing lists. >> >> If you need something to get you going *now*, your best bet is probably to >> reconfigure the O3 model to act like an InOrder model. >> >> If no one takes up the task of adding ARM to InOrder, I'll eventually do >> it >> myself (I want to see the InOrder model be useful to others), but >> currently >> there are other first-order tasks on my plate. >> >> (oh, and for ALPHA_FS there is a patch you can check out on the >> reviewboard >> that will allow you to boot the InOrder model) >> >> On Tue, Jan 10, 2012 at 11:39 AM, Ali Saidi<[email protected]> wrote: >> >> >>> Hi Erik, >>> >>> No one is actively working on it (that I know of at >>> least), but it would be great to have. Korey got the model very close to >>> supporting ALPHA Fullsystem, so the two major things that would need to >>> be added are predicated execution and hardware table walking support. >>> >>> >>> Thanks, >>> >>> Ali >>> >>> On 10.01.2012 10:27, Erik Tomusk wrote: >>> >>> Hello >>>> >>> gem5-dev, >>> >>>> Is anyone working on making the InOrder CPU model work >>>> >>> with ARM? If not, >>> >>>> what would need to be done to make it work? Or does >>>> >>> it make more sense >>> >>>> to just configure the O3CPU model to be more like >>>> >>> an in-order? >>> >>>> Thanks, >>>> Erik >>>> >>> >>> ______________________________**_________________ >>> gem5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/**listinfo/gem5-dev<http://m5sim.org/mailman/listinfo/gem5-dev> >>> >>> >> >> > -- > The University of Edinburgh is a charitable body, registered in > Scotland, with registration number SC005336. > > ______________________________**_________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/**listinfo/gem5-dev<http://m5sim.org/mailman/listinfo/gem5-dev> > -- - Korey _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
