changeset 575cab0db076 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=575cab0db076
description:
SE/FS: Build the Interrupt objects in SE mode.
diffstat:
src/arch/alpha/SConscript | 4 +-
src/arch/arm/SConscript | 4 +-
src/arch/mips/SConscript | 6 +-
src/arch/mips/interrupts.cc | 1 +
src/arch/power/PowerInterrupts.py | 33 +++++++++++
src/arch/power/SConscript | 3 +
src/arch/power/interrupts.cc | 37 +++++++++++++
src/arch/power/interrupts.hh | 105 ++++++++++++++++++++++++++++++++++++++
src/arch/sparc/SConscript | 6 +-
src/arch/x86/SConscript | 6 +-
src/arch/x86/interrupts.cc | 4 +-
src/cpu/BaseCPU.py | 47 ++++++----------
src/cpu/base.cc | 15 +---
src/cpu/base.hh | 14 +---
14 files changed, 221 insertions(+), 64 deletions(-)
diffs (truncated from 628 to 300 lines):
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/alpha/SConscript
--- a/src/arch/alpha/SConscript Sat Oct 08 23:24:34 2011 -0700
+++ b/src/arch/alpha/SConscript Sun Oct 09 00:15:50 2011 -0700
@@ -34,6 +34,7 @@
if env['TARGET_ISA'] == 'alpha':
Source('ev5.cc')
Source('faults.cc')
+ Source('interrupts.cc')
Source('ipr.cc')
Source('isa.cc')
Source('pagetable.cc')
@@ -42,14 +43,13 @@
Source('tlb.cc')
Source('utility.cc')
+ SimObject('AlphaInterrupts.py')
SimObject('AlphaTLB.py')
if env['FULL_SYSTEM']:
- SimObject('AlphaInterrupts.py')
SimObject('AlphaSystem.py')
Source('idle_event.cc')
- Source('interrupts.cc')
Source('kernel_stats.cc')
Source('osfpal.cc')
Source('stacktrace.cc')
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Sat Oct 08 23:24:34 2011 -0700
+++ b/src/arch/arm/SConscript Sun Oct 09 00:15:50 2011 -0700
@@ -54,6 +54,7 @@
Source('insts/pred_inst.cc')
Source('insts/static_inst.cc')
Source('insts/vfp.cc')
+ Source('interrupts.cc')
Source('isa.cc')
Source('miscregs.cc')
Source('predecoder.cc')
@@ -62,6 +63,7 @@
Source('utility.cc')
Source('remote_gdb.cc')
+ SimObject('ArmInterrupts.py')
SimObject('ArmNativeTrace.py')
SimObject('ArmTLB.py')
@@ -70,14 +72,12 @@
DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
DebugFlag('Predecoder', "Instructions returned by the predecoder")
if env['FULL_SYSTEM']:
- Source('interrupts.cc')
Source('stacktrace.cc')
Source('system.cc')
Source('vtophys.cc')
Source('linux/system.cc')
Source('table_walker.cc')
- SimObject('ArmInterrupts.py')
SimObject('ArmSystem.py')
else:
Source('process.cc')
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/mips/SConscript
--- a/src/arch/mips/SConscript Sat Oct 08 23:24:34 2011 -0700
+++ b/src/arch/mips/SConscript Sun Oct 09 00:15:50 2011 -0700
@@ -34,6 +34,7 @@
if env['TARGET_ISA'] == 'mips':
Source('faults.cc')
+ Source('interrupts.cc')
Source('isa.cc')
Source('tlb.cc')
Source('pagetable.cc')
@@ -41,19 +42,18 @@
Source('dsp.cc')
Source('remote_gdb.cc')
+ SimObject('MipsInterrupts.py')
+ DebugFlag('MipsPRA')
SimObject('MipsTLB.py')
- DebugFlag('MipsPRA')
if env['FULL_SYSTEM']:
SimObject('MipsSystem.py')
- SimObject('MipsInterrupts.py')
Source('idle_event.cc')
Source('mips_core_specific.cc')
Source('vtophys.cc')
Source('system.cc')
Source('stacktrace.cc')
Source('linux/system.cc')
- Source('interrupts.cc')
Source('bare_iron/system.cc')
else:
Source('process.cc')
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/mips/interrupts.cc
--- a/src/arch/mips/interrupts.cc Sat Oct 08 23:24:34 2011 -0700
+++ b/src/arch/mips/interrupts.cc Sun Oct 09 00:15:50 2011 -0700
@@ -36,6 +36,7 @@
#include "arch/mips/pra_constants.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
namespace MipsISA
{
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/power/PowerInterrupts.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/power/PowerInterrupts.py Sun Oct 09 00:15:50 2011 -0700
@@ -0,0 +1,33 @@
+# Copyright (c) 2011 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class PowerInterrupts(SimObject):
+ type = 'PowerInterrupts'
+ cxx_class = 'PowerISA::Interrupts'
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/power/SConscript
--- a/src/arch/power/SConscript Sat Oct 08 23:24:34 2011 -0700
+++ b/src/arch/power/SConscript Sun Oct 09 00:15:50 2011 -0700
@@ -40,11 +40,14 @@
Source('insts/floating.cc')
Source('insts/condition.cc')
Source('insts/static_inst.cc')
+ Source('interrupts.cc')
Source('pagetable.cc')
Source('tlb.cc')
Source('utility.cc')
+ SimObject('PowerInterrupts.py')
SimObject('PowerTLB.py')
+
DebugFlag('Power')
if not env['FULL_SYSTEM']:
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/power/interrupts.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/power/interrupts.cc Sun Oct 09 00:15:50 2011 -0700
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/power/interrupts.hh"
+
+PowerISA::Interrupts *
+PowerInterruptsParams::create()
+{
+ return new PowerISA::Interrupts(this);
+}
diff -r cf8fb1aa1b30 -r 575cab0db076 src/arch/power/interrupts.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/power/interrupts.hh Sun Oct 09 00:15:50 2011 -0700
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_INTERRUPT_HH__
+#define __ARCH_POWER_INTERRUPT_HH__
+
+#include "base/misc.hh"
+#include "params/PowerInterrupts.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+namespace PowerISA {
+
+class Interrupts : public SimObject
+{
+ private:
+ BaseCPU * cpu;
+
+ public:
+ typedef PowerInterruptsParams Params;
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
+ Interrupts(Params * p) : SimObject(p), cpu(NULL)
+ {}
+
+ void
+ setCPU(BaseCPU * _cpu)
+ {
+ cpu = _cpu;
+ }
+
+ void
+ post(int int_num, int index)
+ {
+ panic("Interrupts::post not implemented.\n");
+ }
+
+ void
+ clear(int int_num, int index)
+ {
+ panic("Interrupts::clear not implemented.\n");
+ }
+
+ void
+ clearAll()
+ {
+ panic("Interrupts::clearAll not implemented.\n");
+ }
+
+ bool
+ checkInterrupts(ThreadContext *tc) const
+ {
+ panic("Interrupts::checkInterrupts not implemented.\n");
+ }
+
+ Fault
+ getInterrupt(ThreadContext *tc)
+ {
+ panic("Interrupts::getInterrupt not implemented.\n");
+ }
+
+ void
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