changeset a5a83fc04972 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a5a83fc04972
description:
        SE/FS: Remove the last references to FULL_SYSTEM from POWER.

diffstat:

 src/arch/power/SConscript |   8 +++-----
 src/arch/power/tlb.cc     |  17 +++++++++--------
 2 files changed, 12 insertions(+), 13 deletions(-)

diffs (60 lines):

diff -r a2a4416cadc8 -r a5a83fc04972 src/arch/power/SConscript
--- a/src/arch/power/SConscript Sun Oct 30 03:06:40 2011 -0700
+++ b/src/arch/power/SConscript Sun Oct 30 03:55:24 2011 -0700
@@ -41,7 +41,10 @@
     Source('insts/condition.cc')
     Source('insts/static_inst.cc')
     Source('interrupts.cc')
+    Source('linux/linux.cc')
+    Source('linux/process.cc')
     Source('pagetable.cc')
+    Source('process.cc')
     Source('tlb.cc')
     Source('utility.cc')
     Source('vtophys.cc')
@@ -51,11 +54,6 @@
 
     DebugFlag('Power')
 
-    if not env['FULL_SYSTEM']:
-        Source('process.cc')
-        Source('linux/linux.cc')
-        Source('linux/process.cc')
-
     # Add in files generated by the ISA description.
     isa_desc_files = env.ISADesc('isa/main.isa')
 
diff -r a2a4416cadc8 -r a5a83fc04972 src/arch/power/tlb.cc
--- a/src/arch/power/tlb.cc     Sun Oct 30 03:06:40 2011 -0700
+++ b/src/arch/power/tlb.cc     Sun Oct 30 03:55:24 2011 -0700
@@ -50,6 +50,7 @@
 #include "debug/TLB.hh"
 #include "mem/page_table.hh"
 #include "params/PowerTLB.hh"
+#include "sim/full_system.hh"
 #include "sim/process.hh"
 
 using namespace std;
@@ -310,14 +311,14 @@
 Fault
 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
-#if !FULL_SYSTEM
-    if (mode == Execute)
-        return translateInst(req, tc);
-    else
-        return translateData(req, tc, mode == Write);
-#else
-  fatal("translate atomic not yet implemented\n");
-#endif
+    if (FullSystem) {
+        fatal("translate atomic not yet implemented in full system mode.\n");
+    } else {
+        if (mode == Execute)
+            return translateInst(req, tc);
+        else
+            return translateData(req, tc, mode == Write);
+    }
 }
 
 void
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