changeset 2a590c51adb1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2a590c51adb1
description:
SE/FS: Expose the same methods on the CPUs in SE and FS modes.
diffstat:
src/cpu/base.cc | 44 +++++++++++++++---------------------
src/cpu/base.hh | 8 ++----
src/cpu/exec_context.hh | 4 +--
src/cpu/inorder/cpu.cc | 2 -
src/cpu/inorder/cpu.hh | 2 -
src/cpu/inorder/inorder_dyn_inst.cc | 16 +++++-------
src/cpu/inorder/inorder_dyn_inst.hh | 3 --
src/cpu/o3/cpu.cc | 13 ++--------
src/cpu/o3/cpu.hh | 4 ---
src/cpu/o3/dyn_inst.hh | 2 -
src/cpu/o3/dyn_inst_impl.hh | 27 ++++++++++-----------
src/cpu/simple/atomic.cc | 28 ++++++++++++----------
src/cpu/simple/base.cc | 22 ++++--------------
src/cpu/simple/base.hh | 36 +++++++++---------------------
src/cpu/simple/timing.cc | 26 +++++++++++----------
15 files changed, 91 insertions(+), 146 deletions(-)
diffs (truncated from 731 to 300 lines):
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/base.cc
--- a/src/cpu/base.cc Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/base.cc Tue Nov 01 04:01:13 2011 -0700
@@ -47,6 +47,7 @@
#include "cpu/thread_context.hh"
#include "debug/SyscallVerbose.hh"
#include "params/BaseCPU.hh"
+#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
@@ -197,11 +198,13 @@
}
interrupts->setCPU(this);
+ if (FullSystem) {
#if FULL_SYSTEM
- profileEvent = NULL;
- if (params()->profile)
- profileEvent = new ProfileEvent(this, params()->profile);
+ profileEvent = NULL;
+ if (params()->profile)
+ profileEvent = new ProfileEvent(this, params()->profile);
#endif
+ }
tracer = params()->tracer;
}
@@ -225,10 +228,10 @@
void
BaseCPU::startup()
{
-#if FULL_SYSTEM
- if (!params()->defer_registration && profileEvent)
- schedule(profileEvent, curTick());
-#endif
+ if (FullSystem) {
+ if (!params()->defer_registration && profileEvent)
+ schedule(profileEvent, curTick());
+ }
if (params()->progress_interval) {
Tick num_ticks = ticks(params()->progress_interval);
@@ -268,9 +271,6 @@
}
} else if (size == 1)
threadContexts[0]->regStats(name());
-
-#if FULL_SYSTEM
-#endif
}
Tick
@@ -312,9 +312,9 @@
tc->setContextId(system->registerThreadContext(tc, _cpuId));
else
tc->setContextId(system->registerThreadContext(tc));
-#if !FULL_SYSTEM
- tc->getProcessPtr()->assignThreadContext(tc->contextId());
-#endif
+
+ if (!FullSystem)
+ tc->getProcessPtr()->assignThreadContext(tc->contextId());
}
}
@@ -333,11 +333,8 @@
void
BaseCPU::switchOut()
{
-// panic("This CPU doesn't support sampling!");
-#if FULL_SYSTEM
if (profileEvent && profileEvent->scheduled())
deschedule(profileEvent);
-#endif
}
void
@@ -391,13 +388,13 @@
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
-#if FULL_SYSTEM
- for (ThreadID i = 0; i < size; ++i)
- threadContexts[i]->profileClear();
+ if (FullSystem) {
+ for (ThreadID i = 0; i < size; ++i)
+ threadContexts[i]->profileClear();
- if (profileEvent)
- schedule(profileEvent, curTick());
-#endif
+ if (profileEvent)
+ schedule(profileEvent, curTick());
+ }
// Connect new CPU to old CPU's memory only if new CPU isn't
// connected to anything. Also connect old CPU's memory to new
@@ -416,7 +413,6 @@
}
-#if FULL_SYSTEM
BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
: cpu(_cpu), interval(_interval)
{ }
@@ -433,8 +429,6 @@
cpu->schedule(this, curTick() + interval);
}
-#endif // FULL_SYSTEM
-
void
BaseCPU::serialize(std::ostream &os)
{
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/base.hh
--- a/src/cpu/base.hh Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/base.hh Tue Nov 01 04:01:13 2011 -0700
@@ -44,6 +44,7 @@
#include "config/the_isa.hh"
#include "mem/mem_object.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/insttracer.hh"
class BaseCPUParams;
@@ -132,17 +133,14 @@
return interrupts;
}
-#if FULL_SYSTEM
virtual void wakeup() = 0;
-#endif
void
postInterrupt(int int_num, int index)
{
interrupts->post(int_num, index);
-#if FULL_SYSTEM
- wakeup();
-#endif
+ if (FullSystem)
+ wakeup();
}
void
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/exec_context.hh
--- a/src/cpu/exec_context.hh Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/exec_context.hh Tue Nov 01 04:01:13 2011 -0700
@@ -111,7 +111,6 @@
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
-#if FULL_SYSTEM
/** Somewhat Alpha-specific function that handles returning from
* an error or interrupt. */
Fault hwrei();
@@ -121,10 +120,9 @@
* return value is false, actual PAL call will be suppressed.
*/
bool simPalCheck(int palFunc);
-#else
+
/** Executes a syscall specified by the callnum. */
void syscall(int64_t callnum);
-#endif
/** Finish a DTB address translation. */
void finishTranslation(WholeTranslationState *state);
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/inorder/cpu.cc Tue Nov 01 04:01:13 2011 -0700
@@ -1688,7 +1688,6 @@
schedule(&tickEvent, nextCycle(curTick()));
}
-#if FULL_SYSTEM
// Lots of copied full system code...place into BaseCPU class?
void
InOrderCPU::wakeup()
@@ -1701,7 +1700,6 @@
DPRINTF(Quiesce, "Suspended Processor woken\n");
threadContexts[0]->activate();
}
-#endif
void
InOrderCPU::syscallContext(Fault fault, ThreadID tid, DynInstPtr inst, int
delay)
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/inorder/cpu.hh Tue Nov 01 04:01:13 2011 -0700
@@ -751,9 +751,7 @@
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
-#if FULL_SYSTEM
virtual void wakeup();
-#endif
/* LL/SC debug functionality
unsigned stCondFails;
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Tue Nov 01 04:01:13 2011 -0700
@@ -45,6 +45,7 @@
#include "cpu/exetrace.hh"
#include "debug/InOrderDynInst.hh"
#include "mem/request.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace TheISA;
@@ -269,8 +270,6 @@
}
-#if FULL_SYSTEM
-
Fault
InOrderDynInst::hwrei()
{
@@ -311,17 +310,16 @@
#endif
return this->cpu->simPalCheck(palFunc, this->threadNumber);
}
-#endif
void
InOrderDynInst::syscall(int64_t callnum)
{
-#if FULL_SYSTEM
- panic("Syscall emulation isn't available in FS mode.\n");
-#else
- syscallNum = callnum;
- cpu->syscallContext(NoFault, this->threadNumber, this);
-#endif
+ if (FullSystem) {
+ panic("Syscall emulation isn't available in FS mode.\n");
+ } else {
+ syscallNum = callnum;
+ cpu->syscallContext(NoFault, this->threadNumber, this);
+ }
}
void
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Tue Nov 01 04:01:13 2011 -0700
@@ -517,15 +517,12 @@
void setCurResSlot(unsigned slot_num) { curResSlot = slot_num; }
/** Calls a syscall. */
-#if FULL_SYSTEM
/** Calls hardware return from error interrupt. */
Fault hwrei();
/** Traps to handle specified fault. */
void trap(Fault fault);
bool simPalCheck(int palFunc);
-#else
short syscallNum;
-#endif
/** Emulates a syscall. */
void syscall(int64_t callnum);
diff -r fbaf6af0be93 -r 2a590c51adb1 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Mon Oct 31 02:58:24 2011 -0700
+++ b/src/cpu/o3/cpu.cc Tue Nov 01 04:01:13 2011 -0700
@@ -31,6 +31,7 @@
* Rick Strong
*/
+#include "arch/kernel_stats.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "config/use_checker.hh"
@@ -38,6 +39,7 @@
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/thread_context.hh"
#include "cpu/activity.hh"
+#include "cpu/quiesce_event.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Activity.hh"
@@ -45,15 +47,10 @@
#include "debug/Quiesce.hh"
#include "enums/MemoryMode.hh"
#include "sim/core.hh"
+#include "sim/process.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
-#if FULL_SYSTEM
-#include "cpu/quiesce_event.hh"
-#else
-#include "sim/process.hh"
-#endif
-
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#endif
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
