changeset 89e0822462a1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=89e0822462a1
description:
SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
diffstat:
src/arch/alpha/SConscript | 29 ++++-------
src/arch/alpha/ev5.cc | 16 ------
src/arch/alpha/faults.cc | 104 ++++++++++++++++++++++------------------
src/arch/alpha/faults.hh | 13 -----
src/arch/alpha/isa/decoder.isa | 66 ++++++++++++-------------
src/arch/alpha/predecoder.hh | 7 +-
src/arch/alpha/regredir.cc | 9 ---
src/arch/alpha/remote_gdb.cc | 84 ++++++++++++++++----------------
src/arch/alpha/utility.cc | 36 ++++++-------
src/arch/alpha/utility.hh | 3 -
src/cpu/simple/base.cc | 5 +-
src/kern/tru64/tru64.hh | 8 ---
12 files changed, 162 insertions(+), 218 deletions(-)
diffs (truncated from 758 to 300 lines):
diff -r 2a590c51adb1 -r 89e0822462a1 src/arch/alpha/SConscript
--- a/src/arch/alpha/SConscript Tue Nov 01 04:01:13 2011 -0700
+++ b/src/arch/alpha/SConscript Tue Nov 01 04:01:14 2011 -0700
@@ -34,40 +34,33 @@
if env['TARGET_ISA'] == 'alpha':
Source('ev5.cc')
Source('faults.cc')
+ Source('freebsd/system.cc')
+ Source('idle_event.cc')
Source('interrupts.cc')
Source('ipr.cc')
Source('isa.cc')
Source('kernel_stats.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
Source('osfpal.cc')
Source('pagetable.cc')
+ Source('process.cc')
Source('regredir.cc')
Source('remote_gdb.cc')
Source('stacktrace.cc')
+ Source('system.cc')
Source('tlb.cc')
+ Source('tru64/process.cc')
+ Source('tru64/system.cc')
+ Source('tru64/tru64.cc')
Source('utility.cc')
Source('vtophys.cc')
SimObject('AlphaInterrupts.py')
+ SimObject('AlphaSystem.py')
SimObject('AlphaTLB.py')
- if env['FULL_SYSTEM']:
- SimObject('AlphaSystem.py')
-
- Source('idle_event.cc')
- Source('system.cc')
-
- Source('freebsd/system.cc')
- Source('linux/system.cc')
- Source('tru64/system.cc')
-
- else:
- Source('process.cc')
-
- Source('linux/linux.cc')
- Source('linux/process.cc')
-
- Source('tru64/tru64.cc')
- Source('tru64/process.cc')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff -r 2a590c51adb1 -r 89e0822462a1 src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Tue Nov 01 04:01:13 2011 -0700
+++ b/src/arch/alpha/ev5.cc Tue Nov 01 04:01:14 2011 -0700
@@ -44,8 +44,6 @@
namespace AlphaISA {
-#if FULL_SYSTEM
-
////////////////////////////////////////////////////////////////////////
//
// Machine dependent functions
@@ -76,8 +74,6 @@
cpu->thread->setFloatReg(ZeroReg, 0.0);
}
-#endif
-
////////////////////////////////////////////////////////////////////////
//
//
@@ -201,10 +197,8 @@
return retval;
}
-#ifdef DEBUG
// Cause the simulator to break when changing to the following IPL
int break_ipl = -1;
-#endif
void
ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
@@ -264,10 +258,8 @@
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
-#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->context(old, val, tc);
-#endif
break;
case IPR_DTB_PTE:
@@ -294,14 +286,11 @@
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
-#if FULL_SYSTEM
if (tc->getKernelStats())
tc->getKernelStats()->swpipl(ipr[idx]);
-#endif
break;
case IPR_DTB_CM:
-#if FULL_SYSTEM
if (val & 0x18) {
if (tc->getKernelStats())
tc->getKernelStats()->mode(Kernel::user, tc);
@@ -309,7 +298,6 @@
if (tc->getKernelStats())
tc->getKernelStats()->mode(Kernel::kernel, tc);
}
-#endif
case IPR_ICM:
// only write two mode bits - processor mode
@@ -486,8 +474,6 @@
} // namespace AlphaISA
-#if FULL_SYSTEM
-
using namespace AlphaISA;
Fault
@@ -537,5 +523,3 @@
return true;
}
-
-#endif // FULL_SYSTEM
diff -r 2a590c51adb1 -r 89e0822462a1 src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Tue Nov 01 04:01:13 2011 -0700
+++ b/src/arch/alpha/faults.cc Tue Nov 01 04:01:14 2011 -0700
@@ -35,11 +35,9 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-
-#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
+#include "sim/full_system.hh"
namespace AlphaISA {
@@ -107,12 +105,12 @@
FaultVect IntegerOverflowFault::_vect = 0x0501;
FaultStat IntegerOverflowFault::_count;
-#if FULL_SYSTEM
-
void
AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
countStat()++;
PCState pc = tc->pcState();
@@ -135,32 +133,36 @@
ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
panic("Arithmetic traps are unimplemented!");
}
void
DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // Set fault address and flags. Even though we're modeling an
- // EV5, we use the EV6 technique of not latching fault registers
- // on VPTE loads (instead of locking the registers until IPR_VA is
- // read, like the EV5). The EV6 approach is cleaner and seems to
- // work with EV5 PAL code, but not the other way around.
- if (!tc->misspeculating() &&
- reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
- // set VA register with faulting address
- tc->setMiscRegNoEffect(IPR_VA, vaddr);
+ if (FullSystem) {
+ // Set fault address and flags. Even though we're modeling an
+ // EV5, we use the EV6 technique of not latching fault registers
+ // on VPTE loads (instead of locking the registers until IPR_VA is
+ // read, like the EV5). The EV6 approach is cleaner and seems to
+ // work with EV5 PAL code, but not the other way around.
+ if (!tc->misspeculating() &&
+ reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+ // set VA register with faulting address
+ tc->setMiscRegNoEffect(IPR_VA, vaddr);
- // set MM_STAT register flags
- MachInst machInst = inst->machInst;
- tc->setMiscRegNoEffect(IPR_MM_STAT,
- (((Opcode(machInst) & 0x3f) << 11) |
- ((Ra(machInst) & 0x1f) << 6) |
- (flags & 0x3f)));
+ // set MM_STAT register flags
+ MachInst machInst = inst->machInst;
+ tc->setMiscRegNoEffect(IPR_MM_STAT,
+ (((Opcode(machInst) & 0x3f) << 11) |
+ ((Ra(machInst) & 0x1f) << 6) |
+ (flags & 0x3f)));
- // set VA_FORM register with faulting formatted address
- tc->setMiscRegNoEffect(IPR_VA_FORM,
- tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+ // set VA_FORM register with faulting formatted address
+ tc->setMiscRegNoEffect(IPR_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
+ }
}
AlphaFault::invoke(tc);
@@ -169,49 +171,55 @@
void
ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (!tc->misspeculating()) {
- tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
- tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
- tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+ if (FullSystem) {
+ if (!tc->misspeculating()) {
+ tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+ tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+ tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
+ }
}
AlphaFault::invoke(tc);
}
-#else
-
void
ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(pc, entry);
- if (!success) {
- panic("Tried to execute unmapped address %#x.\n", pc);
+ if (FullSystem) {
+ ItbFault::invoke(tc);
} else {
- VAddr vaddr(pc);
- tc->getITBPtr()->insert(vaddr.page(), entry);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(pc, entry);
+ if (!success) {
+ panic("Tried to execute unmapped address %#x.\n", pc);
+ } else {
+ VAddr vaddr(pc);
+ tc->getITBPtr()->insert(vaddr.page(), entry);
+ }
}
}
void
NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- Process *p = tc->getProcessPtr();
- TlbEntry entry;
- bool success = p->pTable->lookup(vaddr, entry);
- if (!success) {
- if (p->fixupStackFault(vaddr))
- success = p->pTable->lookup(vaddr, entry);
- }
- if (!success) {
- panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
+ if (FullSystem) {
+ DtbFault::invoke(tc, inst);
} else {
- tc->getDTBPtr()->insert(vaddr.page(), entry);
+ Process *p = tc->getProcessPtr();
+ TlbEntry entry;
+ bool success = p->pTable->lookup(vaddr, entry);
+ if (!success) {
+ if (p->fixupStackFault(vaddr))
+ success = p->pTable->lookup(vaddr, entry);
+ }
+ if (!success) {
+ panic("Tried to access unmapped address %#x.\n", (Addr)vaddr);
+ } else {
+ tc->getDTBPtr()->insert(vaddr.page(), entry);
+ }
}
}
-#endif
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