changeset 10c9297e14d5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=10c9297e14d5
description:
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
diffstat:
src/arch/arm/SConscript | 15 ++----
src/arch/arm/faults.cc | 77 ++++++++++++++++++---------------
src/arch/arm/faults.hh | 17 ++----
src/arch/arm/insts/static_inst.hh | 7 +-
src/arch/arm/isa/formats/data.isa | 2 -
src/arch/arm/isa/formats/m5ops.isa | 8 ---
src/arch/arm/isa/formats/unimp.isa | 9 +--
src/arch/arm/isa/insts/div.isa | 18 +++----
src/arch/arm/isa/insts/m5ops.isa | 18 --------
src/arch/arm/isa/insts/misc.isa | 51 +++++++++-------------
src/arch/arm/isa/insts/neon.isa | 41 ++++++++---------
src/arch/arm/isa/insts/swap.isa | 9 +--
src/arch/arm/remote_gdb.cc | 46 +++++++++-----------
src/arch/arm/tlb.cc | 29 +++++-------
src/arch/arm/utility.cc | 85 ++++++++++++++++++-------------------
15 files changed, 189 insertions(+), 243 deletions(-)
diffs (truncated from 945 to 300 lines):
diff -r dc1bc37bfb00 -r 10c9297e14d5 src/arch/arm/SConscript
--- a/src/arch/arm/SConscript Tue Nov 01 04:01:15 2011 -0700
+++ b/src/arch/arm/SConscript Wed Nov 02 01:25:15 2011 -0700
@@ -56,11 +56,16 @@
Source('insts/vfp.cc')
Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
Source('miscregs.cc')
Source('nativetrace.cc')
Source('predecoder.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
Source('stacktrace.cc')
+ Source('system.cc')
Source('table_walker.cc')
Source('tlb.cc')
Source('utility.cc')
@@ -68,21 +73,13 @@
SimObject('ArmInterrupts.py')
SimObject('ArmNativeTrace.py')
+ SimObject('ArmSystem.py')
SimObject('ArmTLB.py')
DebugFlag('Arm')
DebugFlag('TLBVerbose')
DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
DebugFlag('Predecoder', "Instructions returned by the predecoder")
- if env['FULL_SYSTEM']:
- Source('system.cc')
- Source('linux/system.cc')
-
- SimObject('ArmSystem.py')
- else:
- Source('process.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff -r dc1bc37bfb00 -r 10c9297e14d5 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Tue Nov 01 04:01:15 2011 -0700
+++ b/src/arch/arm/faults.cc Wed Nov 02 01:25:15 2011 -0700
@@ -47,6 +47,7 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
+#include "sim/full_system.hh"
namespace ArmISA
{
@@ -94,13 +95,13 @@
}
-#if FULL_SYSTEM
-
void
ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
// ARM ARM B1.6.3
FaultBase::invoke(tc);
+ if (!FullSystem)
+ return;
countStat()++;
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
@@ -165,48 +166,54 @@
void
Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- tc->getCpuPtr()->clearInterrupts();
- tc->clearArchRegs();
+ if (FullSystem) {
+ tc->getCpuPtr()->clearInterrupts();
+ tc->clearArchRegs();
+ }
ArmFault::invoke(tc, inst);
}
-#else
-
void
UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // If the mnemonic isn't defined this has to be an unknown instruction.
- assert(unknown || mnemonic != NULL);
- if (disabled) {
- panic("Attempted to execute disabled instruction "
- "'%s' (inst 0x%08x)", mnemonic, machInst);
- } else if (unknown) {
- panic("Attempted to execute unknown instruction (inst 0x%08x)",
- machInst);
+ if (FullSystem) {
+ ArmFault::invoke(tc, inst);
} else {
- panic("Attempted to execute unimplemented instruction "
- "'%s' (inst 0x%08x)", mnemonic, machInst);
+ // If the mnemonic isn't defined this has to be an unknown instruction.
+ assert(unknown || mnemonic != NULL);
+ if (disabled) {
+ panic("Attempted to execute disabled instruction "
+ "'%s' (inst 0x%08x)", mnemonic, machInst);
+ } else if (unknown) {
+ panic("Attempted to execute unknown instruction (inst 0x%08x)",
+ machInst);
+ } else {
+ panic("Attempted to execute unimplemented instruction "
+ "'%s' (inst 0x%08x)", mnemonic, machInst);
+ }
}
}
void
SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- // As of now, there isn't a 32 bit thumb version of this instruction.
- assert(!machInst.bigThumb);
- uint32_t callNum;
- callNum = tc->readIntReg(INTREG_R7);
- tc->syscall(callNum);
+ if (FullSystem) {
+ ArmFault::invoke(tc, inst);
+ } else {
+ // As of now, there isn't a 32 bit thumb version of this instruction.
+ assert(!machInst.bigThumb);
+ uint32_t callNum;
+ callNum = tc->readIntReg(INTREG_R7);
+ tc->syscall(callNum);
- // Advance the PC since that won't happen automatically.
- PCState pc = tc->pcState();
- assert(inst);
- inst->advancePC(pc);
- tc->pcState(pc);
+ // Advance the PC since that won't happen automatically.
+ PCState pc = tc->pcState();
+ assert(inst);
+ inst->advancePC(pc);
+ tc->pcState(pc);
+ }
}
-#endif // FULL_SYSTEM
-
template<class T>
void
AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
@@ -245,13 +252,13 @@
void
ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
DPRINTF(Faults, "Invoking ArmSev Fault\n");
-#if FULL_SYSTEM
- // Set sev_mailbox to 1, clear the pending interrupt from remote
- // SEV execution and let pipeline continue as pcState is still
- // valid.
- tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
- tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
-#endif
+ if (FullSystem) {
+ // Set sev_mailbox to 1, clear the pending interrupt from remote
+ // SEV execution and let pipeline continue as pcState is still
+ // valid.
+ tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
+ tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
+ }
}
// return via SUBS pc, lr, xxx; rfe, movs, ldm
diff -r dc1bc37bfb00 -r 10c9297e14d5 src/arch/arm/faults.hh
--- a/src/arch/arm/faults.hh Tue Nov 01 04:01:15 2011 -0700
+++ b/src/arch/arm/faults.hh Wed Nov 02 01:25:15 2011 -0700
@@ -48,8 +48,8 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
// The design of the "name" and "vect" functions is in sim/faults.hh
@@ -108,10 +108,8 @@
FaultStat count;
};
-#if FULL_SYSTEM
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
virtual FaultStat& countStat() = 0;
virtual FaultOffset offset() = 0;
virtual OperatingMode nextMode() = 0;
@@ -139,19 +137,14 @@
};
class Reset : public ArmFaultVals<Reset>
-#if FULL_SYSTEM
{
public:
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
-#else
-{};
-#endif //FULL_SYSTEM
class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
{
-#if !FULL_SYSTEM
protected:
ExtMachInst machInst;
bool unknown;
@@ -167,25 +160,27 @@
mnemonic(_mnemonic), disabled(_disabled)
{
}
+ UndefinedInstruction() :
+ machInst(0), unknown(false), mnemonic("undefined"), disabled(false)
+ {}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
class SupervisorCall : public ArmFaultVals<SupervisorCall>
{
-#if !FULL_SYSTEM
protected:
ExtMachInst machInst;
public:
SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
{}
+ SupervisorCall() : machInst(0)
+ {}
void invoke(ThreadContext *tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr);
-#endif
};
template <class T>
diff -r dc1bc37bfb00 -r 10c9297e14d5 src/arch/arm/insts/static_inst.hh
--- a/src/arch/arm/insts/static_inst.hh Tue Nov 01 04:01:15 2011 -0700
+++ b/src/arch/arm/insts/static_inst.hh Wed Nov 02 01:25:15 2011 -0700
@@ -46,6 +46,7 @@
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "sim/full_system.hh"
namespace ArmISA
{
@@ -294,11 +295,11 @@
inline Fault
disabledFault() const
{
-#if FULL_SYSTEM
+ if (FullSystem) {
return new UndefinedInstruction();
-#else
+ } else {
return new UndefinedInstruction(machInst, false, mnemonic, true);
-#endif
+ }
}
};
}
diff -r dc1bc37bfb00 -r 10c9297e14d5 src/arch/arm/isa/formats/data.isa
--- a/src/arch/arm/isa/formats/data.isa Tue Nov 01 04:01:15 2011 -0700
+++ b/src/arch/arm/isa/formats/data.isa Wed Nov 02 01:25:15 2011 -0700
@@ -1103,7 +1103,6 @@
switch (IMM) {
case 0x0:
return new NopInst(machInst);
-#if FULL_SYSTEM
case 0x1:
return new YieldInst(machInst);
case 0x2:
@@ -1112,7 +1111,6 @@
return new WfiInst(machInst);
case 0x4:
return new SevInst(machInst);
-#endif
default:
return new Unknown(machInst);
}
diff -r dc1bc37bfb00 -r 10c9297e14d5 src/arch/arm/isa/formats/m5ops.isa
--- a/src/arch/arm/isa/formats/m5ops.isa Tue Nov 01 04:01:15 2011 -0700
+++ b/src/arch/arm/isa/formats/m5ops.isa Wed Nov 02 01:25:15 2011 -0700
@@ -42,35 +42,27 @@
{
const uint32_t m5func = bits(machInst, 23, 16);
switch(m5func) {
-#if FULL_SYSTEM
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