changeset 5f25086326ac in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5f25086326ac
description:
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
diffstat:
src/cpu/BaseCPU.py | 3 +-
src/cpu/SConscript | 7 +-
src/cpu/base.cc | 2 -
src/cpu/base.hh | 2 +-
src/cpu/checker/cpu.cc | 14 +--
src/cpu/checker/cpu.hh | 20 +--
src/cpu/checker/cpu_impl.hh | 46 +++----
src/cpu/checker/thread_context.hh | 9 +-
src/cpu/exetrace.cc | 5 +-
src/cpu/inorder/cpu.cc | 128 ++++++++++-----------
src/cpu/inorder/cpu.hh | 2 -
src/cpu/inorder/inorder_cpu_builder.cc | 20 +-
src/cpu/inorder/params.hh | 2 -
src/cpu/inorder/resources/cache_unit.cc | 5 -
src/cpu/inorder/resources/cache_unit.hh | 3 +-
src/cpu/inorder/resources/execution_unit.cc | 15 +-
src/cpu/inorder/thread_context.cc | 12 +-
src/cpu/inorder/thread_context.hh | 2 -
src/cpu/inorder/thread_state.hh | 12 +-
src/cpu/intr_control.cc | 8 -
src/cpu/legiontrace.cc | 15 +-
src/cpu/o3/O3CPU.py | 14 +-
src/cpu/o3/checker_builder.cc | 3 -
src/cpu/o3/commit.hh | 2 -
src/cpu/o3/commit_impl.hh | 51 +++----
src/cpu/o3/cpu.cc | 113 +++++++++---------
src/cpu/o3/cpu_builder.cc | 31 ++--
src/cpu/o3/decode_impl.hh | 23 +--
src/cpu/o3/fetch_impl.hh | 24 +--
src/cpu/o3/lsq.hh | 2 -
src/cpu/o3/lsq_impl.hh | 2 -
src/cpu/o3/regfile.hh | 7 +-
src/cpu/o3/thread_context_impl.hh | 74 ++++--------
src/cpu/o3/thread_state.hh | 30 ++--
src/cpu/ozone/SimpleOzoneCPU.py | 3 +-
src/cpu/ozone/back_end_impl.hh | 9 -
src/cpu/ozone/checker_builder.cc | 3 -
src/cpu/ozone/cpu.hh | 34 +----
src/cpu/ozone/cpu_builder.cc | 27 +--
src/cpu/ozone/cpu_impl.hh | 163 +++++++++++----------------
src/cpu/ozone/dyn_inst.hh | 3 -
src/cpu/ozone/dyn_inst_impl.hh | 10 +-
src/cpu/ozone/front_end_impl.hh | 6 -
src/cpu/ozone/inorder_back_end.hh | 2 -
src/cpu/ozone/inorder_back_end_impl.hh | 51 +++-----
src/cpu/ozone/lw_back_end_impl.hh | 53 +++------
src/cpu/ozone/simple_cpu_builder.cc | 26 +--
src/cpu/ozone/simple_params.hh | 2 -
src/cpu/ozone/thread_state.hh | 13 +-
src/cpu/pc_event.cc | 3 -
src/cpu/simple/atomic.cc | 4 -
src/cpu/simple/base.cc | 12 +-
src/cpu/simple/timing.cc | 4 -
src/cpu/simple_thread.cc | 75 +++++-------
src/cpu/simple_thread.hh | 5 +-
src/cpu/thread_state.cc | 47 +++----
56 files changed, 487 insertions(+), 776 deletions(-)
diffs (truncated from 3034 to 300 lines):
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/BaseCPU.py Fri Nov 18 01:33:28 2011 -0800
@@ -81,8 +81,7 @@
profile = Param.Latency('0ns', "trace the kernel stack")
do_quiesce = Param.Bool(True, "enable quiesce instructions")
- if not buildEnv['FULL_SYSTEM']:
- workload = VectorParam.Process("processes to run")
+ workload = VectorParam.Process([], "processes to run")
if buildEnv['TARGET_ISA'] == 'sparc':
dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/SConscript
--- a/src/cpu/SConscript Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/SConscript Fri Nov 18 01:33:28 2011 -0800
@@ -129,10 +129,9 @@
Source('thread_context.cc')
Source('thread_state.cc')
-if env['FULL_SYSTEM']:
- if env['TARGET_ISA'] == 'sparc':
- SimObject('LegionTrace.py')
- Source('legiontrace.cc')
+if env['TARGET_ISA'] == 'sparc':
+ SimObject('LegionTrace.py')
+ Source('legiontrace.cc')
if env['USE_CHECKER']:
Source('checker/cpu.cc')
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/base.cc
--- a/src/cpu/base.cc Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/base.cc Fri Nov 18 01:33:28 2011 -0800
@@ -199,11 +199,9 @@
interrupts->setCPU(this);
if (FullSystem) {
-#if FULL_SYSTEM
profileEvent = NULL;
if (params()->profile)
profileEvent = new ProfileEvent(this, params()->profile);
-#endif
}
tracer = params()->tracer;
}
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/base.hh
--- a/src/cpu/base.hh Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/base.hh Fri Nov 18 01:33:28 2011 -0800
@@ -158,7 +158,7 @@
bool
checkInterrupts(ThreadContext *tc) const
{
- return interrupts->checkInterrupts(tc);
+ return FullSystem && interrupts->checkInterrupts(tc);
}
class ProfileEvent : public Event
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/checker/cpu.cc Fri Nov 18 01:33:28 2011 -0800
@@ -31,17 +31,14 @@
#include <list>
#include <string>
+#include "arch/kernel_stats.hh"
+#include "arch/vtophys.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#if FULL_SYSTEM
-#include "arch/kernel_stats.hh"
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
using namespace std;
//The CheckerCPU does alpha only
using namespace AlphaISA;
@@ -66,17 +63,14 @@
exitOnError = p->exitOnError;
warnOnlyOnLoadError = p->warnOnlyOnLoadError;
-#if FULL_SYSTEM
itb = p->itb;
dtb = p->dtb;
systemPtr = NULL;
-#else
process = p->process;
thread = new SimpleThread(this, /* thread_num */ 0, process);
tc = thread->getTC();
threadContexts.push_back(tc);
-#endif
result.integer = 0;
}
@@ -88,7 +82,6 @@
void
CheckerCPU::setSystem(System *system)
{
-#if FULL_SYSTEM
systemPtr = system;
thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
@@ -97,7 +90,6 @@
threadContexts.push_back(tc);
delete thread->kernelStats;
thread->kernelStats = NULL;
-#endif
}
void
@@ -301,13 +293,11 @@
}
-#if FULL_SYSTEM
Addr
CheckerCPU::dbg_vtophys(Addr addr)
{
return vtophys(tc, addr);
}
-#endif // FULL_SYSTEM
bool
CheckerCPU::checkFlags(Request *req)
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/checker/cpu.hh Fri Nov 18 01:33:28 2011 -0800
@@ -46,25 +46,20 @@
#include "sim/eventq.hh"
// forward declarations
-#if FULL_SYSTEM
namespace TheISA
{
class TLB;
}
-class Processor;
-class PhysicalMemory;
-#else
-
-class Process;
-
-#endif // FULL_SYSTEM
template <class>
class BaseDynInst;
class CheckerCPUParams;
+class Checkpoint;
+class MemInterface;
+class PhysicalMemory;
+class Process;
+class Processor;
class ThreadContext;
-class MemInterface;
-class Checkpoint;
class Request;
/**
@@ -129,9 +124,7 @@
TheISA::TLB *itb;
TheISA::TLB *dtb;
-#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
-#endif
union Result {
uint64_t integer;
@@ -273,14 +266,11 @@
this->dtb->demapPage(vaddr, asn);
}
-#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
-#else
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
void syscall(uint64_t callnum) { }
-#endif
void handleError()
{
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/checker/cpu_impl.hh Fri Nov 18 01:33:28 2011 -0800
@@ -31,6 +31,7 @@
#include <list>
#include <string>
+#include "arch/vtophys.hh"
#include "base/refcnt.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
@@ -38,13 +39,10 @@
#include "cpu/simple_thread.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-#if FULL_SYSTEM
-#include "arch/vtophys.hh"
-#endif // FULL_SYSTEM
-
using namespace std;
//The CheckerCPU does alpha only
using namespace AlphaISA;
@@ -141,11 +139,7 @@
// Try to fetch the instruction
-#if FULL_SYSTEM
-#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
-#else
-#define IFETCH_FLAGS(pc) 0
-#endif
+#define IFETCH_FLAGS(pc) (FullSystem ? 0 : ((pc) & 1) ? PHYSICAL : 0)
uint64_t fetch_PC = thread->readPC() & ~3;
@@ -235,12 +229,10 @@
}
if (fault != NoFault) {
-#if FULL_SYSTEM
fault->invoke(tc, curStaticInst);
willChangePC = true;
newPC = thread->readPC();
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
-#endif
} else {
#if THE_ISA != MIPS_ISA
// go to the next instruction
@@ -255,23 +247,23 @@
}
-#if FULL_SYSTEM
- // @todo: Determine if these should happen only if the
- // instruction hasn't faulted. In the SimpleCPU case this may
- // not be true, but in the O3 or Ozone case this may be true.
- Addr oldpc;
- int count = 0;
- do {
- oldpc = thread->readPC();
- system->pcEventQueue.service(tc);
- count++;
- } while (oldpc != thread->readPC());
- if (count > 1) {
- willChangePC = true;
- newPC = thread->readPC();
- DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+ if (FullSystem) {
+ // @todo: Determine if these should happen only if the
+ // instruction hasn't faulted. In the SimpleCPU case this may
+ // not be true, but in the O3 or Ozone case this may be true.
+ Addr oldpc;
+ int count = 0;
+ do {
+ oldpc = thread->readPC();
+ system->pcEventQueue.service(tc);
+ count++;
+ } while (oldpc != thread->readPC());
+ if (count > 1) {
+ willChangePC = true;
+ newPC = thread->readPC();
+ DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+ }
}
-#endif
// @todo: Optionally can check all registers. (Or just those
// that have been modified).
diff -r 1c0812bae427 -r 5f25086326ac src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Sun Nov 13 12:40:15 2011 -0800
+++ b/src/cpu/checker/thread_context.hh Fri Nov 18 01:33:28 2011 -0800
@@ -89,14 +89,13 @@
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
-#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
TheISA::Kernel::Statistics *getKernelStats()
{ return actualTC->getKernelStats(); }
-#endif
+
Process *getProcessPtr() { return actualTC->getProcessPtr(); }
TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
@@ -124,9 +123,7 @@
/// Set the status to Halted.
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