changeset 3202eb01e01e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3202eb01e01e
description:
Another merge with the main repository.
diffstat:
configs/boot/bbench.rcS | 43
+++++++++
configs/common/Benchmarks.py | 5 +-
configs/common/FSConfig.py | 2 +-
configs/common/Options.py | 6 +-
configs/common/Simulation.py | 6 +-
configs/example/se.py | 6 +-
configs/ruby/MOESI_hammer.py | 3 +-
src/arch/arm/nativetrace.cc | 12 ++-
src/arch/x86/tlb.cc | 6 +-
src/base/remote_gdb.cc | 3 +-
src/cpu/o3/fetch_impl.hh | 4 +-
src/dev/i8254xGBe.cc | 7 +-
src/dev/ide_ctrl.cc | 2 +
src/dev/io_device.cc | 8 +-
src/dev/sinic.cc | 5 +-
src/dev/sparc/mm_disk.cc | 32 +++++--
src/dev/terminal.cc | 8 +-
src/mem/page_table.cc | 8 +-
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 6 -
src/mem/protocol/MESI_CMP_directory-dir.sm | 12 ++-
src/mem/protocol/MI_example-dir.sm | 12 ++-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 12 ++-
src/mem/protocol/MOESI_CMP_token-dir.sm | 12 ++-
src/mem/protocol/MOESI_hammer-dir.sm | 12 ++-
src/mem/protocol/RubySlicc_Types.sm | 1 +
src/mem/ruby/common/Set.hh | 16 +++-
src/mem/ruby/eventqueue/RubyEventQueue.cc | 1 -
src/mem/ruby/network/Network.cc | 1 +
src/mem/ruby/network/Network.hh | 3 +-
src/mem/ruby/network/Topology.cc | 1 -
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc | 1 +
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc | 1 +
src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc | 1 +
src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc | 1 +
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc | 1 +
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc | 1 +
src/mem/ruby/network/garnet/flexible-pipeline/Router.cc | 1 +
src/mem/ruby/network/simple/PerfectSwitch.cc | 1 +
src/mem/ruby/network/simple/SimpleNetwork.cc | 1 +
src/mem/ruby/network/simple/Switch.cc | 1 +
src/mem/ruby/network/simple/Throttle.cc | 1 +
src/mem/ruby/slicc_interface/AbstractController.cc | 1 +
src/mem/ruby/slicc_interface/AbstractController.hh | 4 -
src/mem/ruby/slicc_interface/AbstractEntry.hh | 2 -
src/mem/ruby/system/AbstractReplacementPolicy.hh | 2 +-
src/mem/ruby/system/Cache.py | 1 +
src/mem/ruby/system/CacheMemory.cc | 1 +
src/mem/ruby/system/DMASequencer.cc | 1 -
src/mem/ruby/system/DirectoryMemory.cc | 44
+++++----
src/mem/ruby/system/DirectoryMemory.hh | 9 +-
src/mem/ruby/system/MemoryControl.cc | 3 +-
src/mem/ruby/system/MemoryControl.hh | 3 -
src/mem/ruby/system/PersistentTable.hh | 1 -
src/mem/ruby/system/SConscript | 2 +-
src/mem/ruby/system/Sequencer.cc | 10 +-
src/mem/ruby/system/SparseMemory.cc | 35 +++----
src/mem/ruby/system/SparseMemory.hh | 6 +-
src/mem/ruby/system/System.hh | 13 --
src/mem/slicc/ast/FormalParamAST.py | 5 +-
src/mem/slicc/ast/LocalVariableAST.py | 4 +-
src/mem/slicc/ast/MemberExprAST.py | 5 +-
src/mem/slicc/ast/MethodCallExprAST.py | 6 +-
src/mem/slicc/ast/PeekStatementAST.py | 2 +-
src/mem/slicc/symbols/StateMachine.py | 8 +-
src/sim/eventq.cc | 8 +
src/sim/eventq.hh | 10 ++
util/hgfilesize.py | 32 +++++++
67 files changed, 313 insertions(+), 171 deletions(-)
diffs (truncated from 1410 to 300 lines):
diff -r a2ae5c378d0a -r 3202eb01e01e configs/boot/bbench.rcS
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/configs/boot/bbench.rcS Sat Jan 07 02:16:37 2012 -0800
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+#Author: Anthony Gutierrez
+
+stop_m5() {
+ echo "FINISHED";
+ /sbin/m5 exit
+
+ return
+}
+
+wait_bb_finishfifo() {
+ echo "<html><head>FINISH</head><body><h1>FINISH</h1></body></html>" >
/data/bbench/finish_fifo.html
+
+ return
+}
+
+mkfifo_bbench() {
+ mkfifo /data/bbench/finish_fifo.html
+
+ return
+}
+
+run_bbench_test() {
+ echo "STARTING BBENCH"
+
+ mkfifo_bbench
+
+ am start -n com.android.browser/.BrowserActivity
+ wait_bb_finishfifo
+
+ echo "END OF BBENCH RUN"
+
+ rm /data/bbench/finish_fifo.html
+ stop_m5
+
+ return
+}
+
+sleep 10
+/sbin/m5 dumpstats
+/sbin/m5 resetstats
+run_bbench_test
diff -r a2ae5c378d0a -r 3202eb01e01e configs/common/Benchmarks.py
--- a/configs/common/Benchmarks.py Sat Jan 07 02:15:35 2012 -0800
+++ b/configs/common/Benchmarks.py Sat Jan 07 02:16:37 2012 -0800
@@ -111,7 +111,10 @@
'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],
'MutexTest': [SysConfig('mutex-test.rcS', '128MB')],
- 'ArmAndroid': [SysConfig('null.rcS', '256MB', 'android-mbr.img')],
+ 'ArmAndroid': [SysConfig('null.rcS', '256MB',
+
'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img)')],
+ 'bbench': [SysConfig('bbench.rcS', '256MB',
+ 'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img')]
}
benchs = Benchmarks.keys()
diff -r a2ae5c378d0a -r 3202eb01e01e configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Sat Jan 07 02:15:35 2012 -0800
+++ b/configs/common/FSConfig.py Sat Jan 07 02:16:37 2012 -0800
@@ -252,7 +252,7 @@
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
- if mdesc.disk().count('android'):
+ if mdesc.disk().lower().count('android'):
boot_flags += " init=/init "
self.boot_osflags = boot_flags
diff -r a2ae5c378d0a -r 3202eb01e01e configs/common/Options.py
--- a/configs/common/Options.py Sat Jan 07 02:15:35 2012 -0800
+++ b/configs/common/Options.py Sat Jan 07 02:16:37 2012 -0800
@@ -27,9 +27,9 @@
# Authors: Lisa Hsu
# system options
-parser.add_option("-d", "--detailed", action="store_true")
-parser.add_option("-t", "--timing", action="store_true")
-parser.add_option("--inorder", action="store_true")
+parser.add_option("-c", "--cpu-type", type="choice", default="atomic",
+ choices = ["atomic", "timing", "detailed", "inorder"],
+ help = "type of cpu to run with")
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
diff -r a2ae5c378d0a -r 3202eb01e01e configs/common/Simulation.py
--- a/configs/common/Simulation.py Sat Jan 07 02:15:35 2012 -0800
+++ b/configs/common/Simulation.py Sat Jan 07 02:16:37 2012 -0800
@@ -40,14 +40,14 @@
def setCPUClass(options):
atomic = False
- if options.timing:
+ if options.cpu_type == "timing":
class TmpClass(TimingSimpleCPU): pass
- elif options.detailed:
+ elif options.cpu_type == "detailed":
if not options.caches:
print "O3 CPU must be used with caches"
sys.exit(1)
class TmpClass(DerivO3CPU): pass
- elif options.inorder:
+ elif options.cpu_type == "inorder":
if not options.caches:
print "InOrder CPU must be used with caches"
sys.exit(1)
diff -r a2ae5c378d0a -r 3202eb01e01e configs/example/se.py
--- a/configs/example/se.py Sat Jan 07 02:15:35 2012 -0800
+++ b/configs/example/se.py Sat Jan 07 02:16:37 2012 -0800
@@ -122,7 +122,7 @@
workloads = options.cmd
numThreads = 1
-if options.detailed or options.inorder:
+if options.cpu_type == "detailed" or options.cpu_type == "inorder":
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
@@ -154,10 +154,10 @@
numThreads = len(workloads)
if options.ruby:
- if options.detailed:
+ if options.cpu_type == "detailed":
print >> sys.stderr, "Ruby only works with TimingSimpleCPU!!"
sys.exit(1)
- elif not options.timing:
+ elif not options.cpu_type == "timing":
print >> sys.stderr, "****WARN: using Timing CPU since it's needed by
Ruby"
class CPUClass(TimingSimpleCPU): pass
diff -r a2ae5c378d0a -r 3202eb01e01e configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Sat Jan 07 02:15:35 2012 -0800
+++ b/configs/ruby/MOESI_hammer.py Sat Jan 07 02:16:37 2012 -0800
@@ -88,7 +88,8 @@
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
- start_index_bit = block_size_bits)
+ start_index_bit = block_size_bits,
+ is_icache = True)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
diff -r a2ae5c378d0a -r 3202eb01e01e src/arch/arm/nativetrace.cc
--- a/src/arch/arm/nativetrace.cc Sat Jan 07 02:15:35 2012 -0800
+++ b/src/arch/arm/nativetrace.cc Sat Jan 07 02:16:37 2012 -0800
@@ -156,18 +156,23 @@
// Regular int regs
for (int i = 0; i < STATE_NUMVALS; i++) {
if (nState.changed[i] || mState.changed[i]) {
- const char *vergence = " ";
bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
bool newMatch = (mState.newState[i] == nState.newState[i]);
if (oldMatch && newMatch) {
// The more things change, the more they stay the same.
continue;
- } else if (oldMatch && !newMatch) {
+ }
+
+ errorFound = true;
+
+#ifndef NDEBUG
+ const char *vergence = " ";
+ if (oldMatch && !newMatch) {
vergence = "<>";
} else if (!oldMatch && newMatch) {
vergence = "><";
}
- errorFound = true;
+
if (!nState.changed[i]) {
DPRINTF(ExecRegDelta, "%s [%5s] "\
"Native: %#010x "\
@@ -190,6 +195,7 @@
nState.oldState[i], nState.newState[i],
mState.oldState[i], mState.newState[i]);
}
+#endif
}
}
if (errorFound) {
diff -r a2ae5c378d0a -r 3202eb01e01e src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Sat Jan 07 02:15:35 2012 -0800
+++ b/src/arch/x86/tlb.cc Sat Jan 07 02:16:37 2012 -0800
@@ -322,6 +322,9 @@
DPRINTF(TLB, "Miss was serviced.\n");
}
}
+
+ DPRINTF(TLB, "Entry found with paddr %#x, "
+ "doing protection checks.\n", entry->paddr);
// Do paging protection checks.
bool inUser = (m5Reg.cpl == 3 &&
!(flags & (CPL0FlagBit << FlagShift)));
@@ -339,9 +342,6 @@
return new PageFault(vaddr, true, Write, inUser, false);
}
-
- DPRINTF(TLB, "Entry found with paddr %#x, "
- "doing protection checks.\n", entry->paddr);
Addr paddr = entry->paddr | (vaddr & (entry->size-1));
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
req->setPaddr(paddr);
diff -r a2ae5c378d0a -r 3202eb01e01e src/base/remote_gdb.cc
--- a/src/base/remote_gdb.cc Sat Jan 07 02:15:35 2012 -0800
+++ b/src/base/remote_gdb.cc Sat Jan 07 02:16:37 2012 -0800
@@ -644,8 +644,7 @@
bufferSize = gdbregs.bytes() * 2 + 256;
buffer = (char*)malloc(bufferSize);
- TheISA::PCState pc = context->pcState();
- DPRINTF(GDBMisc, "trap: PC=%s\n", pc);
+ DPRINTF(GDBMisc, "trap: PC=%s\n", context->pcState());
clearSingleStep();
diff -r a2ae5c378d0a -r 3202eb01e01e src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sat Jan 07 02:15:35 2012 -0800
+++ b/src/cpu/o3/fetch_impl.hh Sat Jan 07 02:16:37 2012 -0800
@@ -1051,8 +1051,8 @@
if (fetchStatus[tid] != Squashing) {
- TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
- DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
+ DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
+ fromDecode->decodeInfo[tid].nextPC);
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
fromDecode->decodeInfo[tid].squashInst,
diff -r a2ae5c378d0a -r 3202eb01e01e src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc Sat Jan 07 02:15:35 2012 -0800
+++ b/src/dev/i8254xGBe.cc Sat Jan 07 02:16:37 2012 -0800
@@ -2118,11 +2118,12 @@
// iteration we'll get the rest of the data
if (txPacket && txDescCache.packetAvailable()
&& !txDescCache.packetMultiDesc() && txPacket->length) {
- bool success;
-
anQ("TXS", "TX FIFO Q");
DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
- success = txFifo.push(txPacket);
+#ifndef NDEBUG
+ bool success =
+#endif
+ txFifo.push(txPacket);
txFifoTick = true && !drainEvent;
assert(success);
txPacket = NULL;
diff -r a2ae5c378d0a -r 3202eb01e01e src/dev/ide_ctrl.cc
--- a/src/dev/ide_ctrl.cc Sat Jan 07 02:15:35 2012 -0800
+++ b/src/dev/ide_ctrl.cc Sat Jan 07 02:16:37 2012 -0800
@@ -490,6 +490,7 @@
panic("IDE controller access to invalid address: %#x\n", addr);
}
+#ifndef NDEBUG
uint32_t data;
if (pkt->getSize() == 1)
data = pkt->get<uint8_t>();
@@ -499,6 +500,7 @@
data = pkt->get<uint32_t>();
DPRINTF(IdeCtrl, "%s from offset: %#x size: %#x data: %#x\n",
read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(), data);
+#endif
pkt->makeAtomicResponse();
}
diff -r a2ae5c378d0a -r 3202eb01e01e src/dev/io_device.cc
--- a/src/dev/io_device.cc Sat Jan 07 02:15:35 2012 -0800
+++ b/src/dev/io_device.cc Sat Jan 07 02:16:37 2012 -0800
@@ -142,13 +142,9 @@
pkt->reinitNacked();
queueDma(pkt, true);
+ } else if (pkt->isRequest() && recvSnoops) {
+ return true;
} else if (pkt->senderState) {
- if (recvSnoops) {
- if (pkt->isRequest()) {
- return true;
- }
- }
-
DmaReqState *state;
backoffTime >>= 2;
diff -r a2ae5c378d0a -r 3202eb01e01e src/dev/sinic.cc
--- a/src/dev/sinic.cc Sat Jan 07 02:15:35 2012 -0800
+++ b/src/dev/sinic.cc Sat Jan 07 02:16:37 2012 -0800
@@ -33,6 +33,7 @@
#include <string>
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