changeset adaa92be9037 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=adaa92be9037
description:
Merge yet again with the main repository.
diffstat:
SConstruct
| 12 +-
configs/common/FSConfig.py
| 9 +
configs/common/Options.py
| 9 +-
configs/common/Simulation.py
| 10 +-
configs/common/cpu2000.py
| 2 +-
configs/example/fs.py
| 7 +-
configs/ruby/Ruby.py
| 6 +-
ext/libelf/SConscript
| 2 +-
src/SConscript
| 2 +-
src/arch/arm/isa/insts/m5ops.isa
| 7 +-
src/arch/mips/faults.cc
| 4 +-
src/arch/mips/faults.hh
| 14 +-
src/arch/mips/isa/decoder.isa
| 2 +-
src/arch/mips/linux/process.cc
| 2 +-
src/arch/mips/registers.hh
| 2 +-
src/arch/mips/tlb.cc
| 14 +-
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
| 8 +
src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
| 8 +
src/base/hostinfo.cc
| 32 +-
src/base/hostinfo.hh
| 8 +-
src/base/random.cc
| 11 +-
src/base/statistics.hh
| 5 +
src/base/stats/info.hh
| 1 +
src/base/stats/text.cc
| 15 +-
src/cpu/base.hh
| 9 +-
src/cpu/inorder/resources/mult_div_unit.cc
| 1 +
src/cpu/o3/commit_impl.hh
| 3 +
src/cpu/o3/decode_impl.hh
| 4 -
src/cpu/o3/iew_impl.hh
| 6 +-
src/cpu/o3/rename_impl.hh
| 4 -
src/cpu/pc_event.cc
| 6 +-
src/cpu/testers/directedtest/DirectedGenerator.hh
| 2 +-
src/cpu/testers/directedtest/InvalidateGenerator.cc
| 2 +-
src/cpu/testers/directedtest/InvalidateGenerator.hh
| 8 +-
src/cpu/testers/directedtest/RubyDirectedTester.hh
| 4 +-
src/cpu/testers/directedtest/SeriesRequestGenerator.cc
| 2 +-
src/cpu/testers/directedtest/SeriesRequestGenerator.hh
| 6 +-
src/dev/arm/pl111.cc
| 2 +-
src/dev/io_device.cc
| 2 +-
src/mem/SConscript
| 7 +-
src/mem/bus.cc
| 15 +-
src/mem/packet.cc
| 112 +-
src/mem/packet.hh
| 15 +-
src/mem/protocol/MOESI_hammer-cache.sm
| 3 +-
src/mem/ruby/buffers/MessageBuffer.cc
| 6 +-
src/mem/ruby/eventqueue/RubyEventQueue.hh
| 4 -
src/mem/ruby/recorder/CacheRecorder.cc
| 166 +-
src/mem/ruby/recorder/CacheRecorder.hh
| 80 +-
src/mem/ruby/recorder/SConscript
| 4 -
src/mem/ruby/recorder/TraceRecord.cc
| 139 -
src/mem/ruby/recorder/TraceRecord.hh
| 91 -
src/mem/ruby/recorder/Tracer.cc
| 135 -
src/mem/ruby/recorder/Tracer.hh
| 86 -
src/mem/ruby/recorder/Tracer.py
| 37 -
src/mem/ruby/slicc_interface/AbstractController.hh
| 5 +-
src/mem/ruby/system/CacheMemory.cc
| 49 +-
src/mem/ruby/system/CacheMemory.hh
| 16 +-
src/mem/ruby/system/DMASequencer.hh
| 3 +
src/mem/ruby/system/DirectoryMemory.cc
| 1 +
src/mem/ruby/system/MemoryVector.hh
| 86 +-
src/mem/ruby/system/PerfectCacheMemory.hh
| 14 -
src/mem/ruby/system/RubyPort.cc
| 86 +-
src/mem/ruby/system/RubyPort.hh
| 15 +-
src/mem/ruby/system/Sequencer.cc
| 19 +-
src/mem/ruby/system/Sequencer.hh
| 14 +-
src/mem/ruby/system/SparseMemory.cc
| 98 +-
src/mem/ruby/system/SparseMemory.hh
| 27 +-
src/mem/ruby/system/System.cc
| 246 ++-
src/mem/ruby/system/System.hh
| 52 +-
src/mem/slicc/symbols/StateMachine.py
| 31 +
src/python/m5/SimObject.py
| 53 +-
src/python/m5/main.py
| 3 +-
src/python/m5/params.py
| 12 +
src/python/m5/simulate.py
| 12 +
src/sim/System.py
| 2 +-
src/sim/pseudo_inst.cc
| 2 +
src/sim/system.cc
| 50 +-
src/sim/system.hh
| 14 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
| 5 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
| 62 +-
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini
| 5 +-
tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr
| 3 -
tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
| 18 +-
tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
| 42 +-
tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini
| 5 +-
tests/long/00.gzip/ref/x86/linux/simple-timing/simerr
| 3 -
tests/long/00.gzip/ref/x86/linux/simple-timing/simout
| 18 +-
tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
| 394 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
| 8 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
| 10 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 46 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
| 0
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 8 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
| 10 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 46 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
| 7 +-
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
| 13 +-
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1141 +++++----
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
| 4 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
| 5 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 8 +-
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini
| 7 +-
tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
| 3 -
tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
| 18 +-
tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
| 42 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini
| 7 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
| 3 -
tests/long/10.mcf/ref/x86/linux/simple-timing/simout
| 18 +-
tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 394 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
| 5 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout
| 8 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
| 40 +-
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/20.parser/ref/x86/linux/o3-timing/simout
| 7 +-
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
| 704 +++---
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini
| 7 +-
tests/long/20.parser/ref/x86/linux/simple-atomic/simerr
| 3 -
tests/long/20.parser/ref/x86/linux/simple-atomic/simout
| 18 +-
tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
| 42 +-
tests/long/20.parser/ref/x86/linux/simple-timing/config.ini
| 7 +-
tests/long/20.parser/ref/x86/linux/simple-timing/simerr
| 3 -
tests/long/20.parser/ref/x86/linux/simple-timing/simout
| 18 +-
tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
| 394 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini
| 5 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr
| 3 -
tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
| 18 +-
tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
| 42 +-
tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini
| 5 +-
tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr
| 3 -
tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
| 18 +-
tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 394 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
| 7 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 8 +-
tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini
| 5 +-
tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
| 3 -
tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
| 22 +-
tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
| 42 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini
| 5 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/simerr
| 3 -
tests/long/70.twolf/ref/x86/linux/simple-timing/simout
| 22 +-
tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 394 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
| 94 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
| 140 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
| 1 -
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
| 18 +-
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
| 98 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
| 94 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
| 130 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
| 2 -
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
| 18 +-
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
| 98 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/simout
| 6 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
| 80 +-
tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
| 3 +-
tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
| 3 -
tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
| 18 +-
tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
| 42 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
| 124 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
| 69 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr
| 3 -
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
| 18 +-
tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
| 42 +-
tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
| 3 +-
tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
| 3 -
tests/quick/00.hello/ref/x86/linux/simple-timing/simout
| 18 +-
tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
| 386 +-
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
| 119 +-
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
| 8 -
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
| 21 +-
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
| 450 +-
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
| 119 +-
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
| 8 -
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
| 19 +-
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 12 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
| 26 +
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
| 1013 ++++----
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
| 146 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
| 12 +-
tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
| 42 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
| 5 +
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
| 318 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
| 12 +-
tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
| 10 +-
util/hgfilesize.py
| 2 +
util/m5/m5.c
| 16 +-
190 files changed, 5555 insertions(+), 4999 deletions(-)
diffs (truncated from 16398 to 300 lines):
diff -r 3202eb01e01e -r adaa92be9037 SConstruct
--- a/SConstruct Sat Jan 07 02:16:37 2012 -0800
+++ b/SConstruct Mon Jan 16 04:27:10 2012 -0800
@@ -663,10 +663,14 @@
py_libs = []
for lib in py_getvar('LIBS').split() + py_getvar('SYSLIBS').split():
- assert lib.startswith('-l')
- lib = lib[2:]
- if lib not in py_libs:
- py_libs.append(lib)
+ if not lib.startswith('-l'):
+ # Python requires some special flags to link (e.g. -framework
+ # common on OS X systems), assume appending preserves order
+ main.Append(LINKFLAGS=[lib])
+ else:
+ lib = lib[2:]
+ if lib not in py_libs:
+ py_libs.append(lib)
py_libs.append(py_version)
main.Append(CPPPATH=py_includes)
diff -r 3202eb01e01e -r adaa92be9037 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Sat Jan 07 02:16:37 2012 -0800
+++ b/configs/common/FSConfig.py Mon Jan 16 04:27:10 2012 -0800
@@ -483,6 +483,15 @@
self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
+ if hasattr(testSystem, 'realview'):
+ self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
+ self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
+ elif hasattr(testSystem, 'tsunami'):
+ self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
+ self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
+ else:
+ fatal("Don't know how to connect these system together")
+
if dumpfile:
self.etherdump = EtherDump(file=dumpfile)
self.etherlink.dump = Parent.etherdump
diff -r 3202eb01e01e -r adaa92be9037 configs/common/Options.py
--- a/configs/common/Options.py Sat Jan 07 02:16:37 2012 -0800
+++ b/configs/common/Options.py Mon Jan 16 04:27:10 2012 -0800
@@ -27,7 +27,7 @@
# Authors: Lisa Hsu
# system options
-parser.add_option("-c", "--cpu-type", type="choice", default="atomic",
+parser.add_option("--cpu-type", type="choice", default="atomic",
choices = ["atomic", "timing", "detailed", "inorder"],
help = "type of cpu to run with")
parser.add_option("-n", "--num-cpus", type="int", default=1)
@@ -63,7 +63,8 @@
help="exit at specified work end count")
parser.add_option("--work-begin-exit-count", action="store", type="int",
help="exit at specified work begin count")
-
+parser.add_option("--init-param", action="store", type="int", default=0,
+ help="Parameter available in simulation with m5 initparam")
# Checkpointing options
###Note that performing checkpointing via python script files will override
@@ -84,6 +85,10 @@
help="checkpoint at specified work end count")
parser.add_option("--work-cpus-checkpoint-count", action="store", type="int",
help="checkpoint and exit when active cpu count is reached")
+parser.add_option("--restore-with-cpu", action="store", type="choice",
+ default="atomic", choices = ["atomic", "timing",
+ "detailed", "inorder"],
+ help = "cpu type for restoring from a checkpoint")
# CPU Switching - default switch model goes from a checkpoint
diff -r 3202eb01e01e -r adaa92be9037 configs/common/Simulation.py
--- a/configs/common/Simulation.py Sat Jan 07 02:16:37 2012 -0800
+++ b/configs/common/Simulation.py Mon Jan 16 04:27:10 2012 -0800
@@ -60,7 +60,15 @@
test_mem_mode = 'atomic'
if not atomic:
- if options.checkpoint_restore != None or options.fast_forward:
+ if options.checkpoint_restore != None:
+ if options.restore_with_cpu != options.cpu_type:
+ CPUClass = TmpClass
+ class TmpClass(AtomicSimpleCPU): pass
+ else:
+ if options.restore_with_cpu != "atomic":
+ test_mem_mode = 'timing'
+
+ elif options.fast_forward:
CPUClass = TmpClass
class TmpClass(AtomicSimpleCPU): pass
else:
diff -r 3202eb01e01e -r adaa92be9037 configs/common/cpu2000.py
--- a/configs/common/cpu2000.py Sat Jan 07 02:16:37 2012 -0800
+++ b/configs/common/cpu2000.py Mon Jan 16 04:27:10 2012 -0800
@@ -731,7 +731,7 @@
'-first_iter_pres_fac', '4', '-initial_pres_fac', '8' ]
output = 'route_log.out'
-all = [ ammp, applu, apsi, art110, art470, equake, facerec, fma3d, galgel,
+all = [ ammp, applu, apsi, art, art110, art470, equake, facerec, fma3d, galgel,
lucas, mesa, mgrid, sixtrack, swim, wupwise, bzip2_source,
bzip2_graphic, bzip2_program, crafty, eon_kajiya, eon_cook,
eon_rushmeier, gap, gcc_166, gcc_200, gcc_expr, gcc_integrate,
diff -r 3202eb01e01e -r adaa92be9037 configs/example/fs.py
--- a/configs/example/fs.py Sat Jan 07 02:16:37 2012 -0800
+++ b/configs/example/fs.py Mon Jan 16 04:27:10 2012 -0800
@@ -151,6 +151,8 @@
if options.script is not None:
test_sys.readfile = options.script
+test_sys.init_param = options.init_param
+
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
CacheConfig.config_cache(options, test_sys)
@@ -190,8 +192,8 @@
elif buildEnv['TARGET_ISA'] == 'x86':
drive_sys = makeX86System(drive_mem_mode, np, bm[1])
elif buildEnv['TARGET_ISA'] == 'arm':
- drive_sys = makeArmSystem(drive_mem_mode,
- machine_options.machine_type, bm[1])
+ drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
+
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectAllPorts(drive_sys.membus)
if options.fastmem:
@@ -199,6 +201,7 @@
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
+ drive_sys.init_param = options.init_param
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
root = Root(system=test_sys)
diff -r 3202eb01e01e -r adaa92be9037 configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Sat Jan 07 02:16:37 2012 -0800
+++ b/configs/ruby/Ruby.py Mon Jan 16 04:27:10 2012 -0800
@@ -67,7 +67,8 @@
def create_system(options, system, piobus = None, dma_devices = []):
system.ruby = RubySystem(clock = options.clock,
- stats_filename = options.ruby_stats)
+ stats_filename = options.ruby_stats,
+ no_mem_vec = options.use_map)
ruby = system.ruby
protocol = buildEnv['PROTOCOL']
@@ -154,11 +155,8 @@
ruby_profiler = RubyProfiler(ruby_system = ruby,
num_of_sequencers = len(cpu_sequencers))
- ruby_tracer = RubyTracer(ruby_system = ruby)
-
ruby.network = network
ruby.profiler = ruby_profiler
- ruby.tracer = ruby_tracer
ruby.mem_size = total_mem_size
ruby._cpu_ruby_ports = cpu_sequencers
ruby.random_seed = options.random_seed
diff -r 3202eb01e01e -r adaa92be9037 ext/libelf/SConscript
--- a/ext/libelf/SConscript Sat Jan 07 02:16:37 2012 -0800
+++ b/ext/libelf/SConscript Mon Jan 16 04:27:10 2012 -0800
@@ -91,7 +91,7 @@
m4env = main.Clone()
if m4env['GCC']:
- major,minor,dot = [ int(x) for x in m4env['CXXVERSION'].split('.')]
+ major,minor,dot = [int(x) for x in m4env['GCC_VERSION'].split('.')]
if major >= 4:
m4env.Append(CCFLAGS=['-Wno-pointer-sign'])
m4env.Append(CCFLAGS=['-Wno-implicit'])
diff -r 3202eb01e01e -r adaa92be9037 src/SConscript
--- a/src/SConscript Sat Jan 07 02:16:37 2012 -0800
+++ b/src/SConscript Mon Jan 16 04:27:10 2012 -0800
@@ -851,8 +851,8 @@
swig_env.Append(CCFLAGS='-Wno-uninitialized')
swig_env.Append(CCFLAGS='-Wno-sign-compare')
swig_env.Append(CCFLAGS='-Wno-parentheses')
+ swig_env.Append(CCFLAGS='-Wno-unused-label')
if compareVersions(env['GCC_VERSION'], '4.6.0') != -1:
- swig_env.Append(CCFLAGS='-Wno-unused-label')
swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
werror_env = new_env.Clone()
diff -r 3202eb01e01e -r adaa92be9037 src/arch/arm/isa/insts/m5ops.isa
--- a/src/arch/arm/isa/insts/m5ops.isa Sat Jan 07 02:16:37 2012 -0800
+++ b/src/arch/arm/isa/insts/m5ops.isa Mon Jan 16 04:27:10 2012 -0800
@@ -190,12 +190,15 @@
exec_output += PredOpExecute.subst(loadsymbolIop)
initparamCode = '''
- Rt = PseudoInst::initParam(xc->tcBase());
+ uint64_t ip_val = PseudoInst::initParam(xc->tcBase());
+ R0 = bits(ip_val, 31, 0);
+ R1 = bits(ip_val, 63, 32);
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
{ "code": initparamCode,
- "predicate_test": predicateTest })
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative"])
header_output += BasicDeclare.subst(initparamIop)
decoder_output += BasicConstructor.subst(initparamIop)
exec_output += PredOpExecute.subst(initparamIop)
diff -r 3202eb01e01e -r adaa92be9037 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Sat Jan 07 02:16:37 2012 -0800
+++ b/src/arch/mips/faults.cc Mon Jan 16 04:27:10 2012 -0800
@@ -29,6 +29,8 @@
* Authors: Gabe Black
* Korey Sewell
* Jaidev Patwardhan
+ * Zhengxing Li
+ * Deyuan Guo
*/
#include "arch/mips/faults.hh"
@@ -118,7 +120,7 @@
DPRINTF(MipsPRA, "PC: %s\n", pc);
bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc();
tc->setMiscRegNoEffect(MISCREG_EPC,
- pc.pc() - delay_slot ? sizeof(MachInst) : 0);
+ pc.pc() - (delay_slot ? sizeof(MachInst) : 0));
// Set Cause_EXCCODE field
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
diff -r 3202eb01e01e -r adaa92be9037 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh Sat Jan 07 02:16:37 2012 -0800
+++ b/src/arch/mips/faults.hh Mon Jan 16 04:27:10 2012 -0800
@@ -29,6 +29,8 @@
* Authors: Gabe Black
* Korey Sewell
* Jaidev Patwardhan
+ * Zhengxing Li
+ * Deyuan Guo
*/
#ifndef __MIPS_FAULTS_HH__
@@ -88,7 +90,7 @@
virtual FaultVect base(ThreadContext *tc) const
{
StatusReg status = tc->readMiscReg(MISCREG_STATUS);
- if (status.bev)
+ if (!status.bev)
return tc->readMiscReg(MISCREG_EBASE);
else
return 0xbfc00200;
@@ -167,7 +169,7 @@
if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID;
- tc->setMiscReg(MISCREG_CAUSE, cause);
+ tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
}
}
};
@@ -179,7 +181,8 @@
offset(ThreadContext *tc) const
{
CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
- return cause.iv ? 0x200 : 0x000;
+ // offset 0x200 for release 2, 0x180 for release 1.
+ return cause.iv ? 0x200 : 0x180;
}
};
@@ -251,9 +254,10 @@
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
if (FullSystem) {
- DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
- tc->pcState(this->vect(tc));
+ DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
+ Addr vect = this->vect(tc);
setTlbExceptionState(tc, this->code());
+ tc->pcState(vect);
} else {
AddressFault<T>::invoke(tc, inst);
}
diff -r 3202eb01e01e -r adaa92be9037 src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Sat Jan 07 02:16:37 2012 -0800
+++ b/src/arch/mips/isa/decoder.isa Mon Jan 16 04:27:10 2012 -0800
@@ -1253,7 +1253,7 @@
//When rs=L1
//Note: "1. Format type L is legal only if 64-bit
//floating point operations are enabled."
- 0x5: decode FUNCTION_HI {
+ 0x5: decode FUNCTION {
format FloatConvertOp {
0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle);
0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble);
diff -r 3202eb01e01e -r adaa92be9037 src/arch/mips/linux/process.cc
--- a/src/arch/mips/linux/process.cc Sat Jan 07 02:16:37 2012 -0800
+++ b/src/arch/mips/linux/process.cc Mon Jan 16 04:27:10 2012 -0800
@@ -55,7 +55,7 @@
strcpy(name->sysname, "Linux");
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