changeset 35e77c938919 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=35e77c938919
description:
Yet another merge with the main repository.
diffstat:
configs/example/ruby_fs.py
| 17 +-
src/cpu/o3/O3CPU.py
| 2 +
src/cpu/o3/lsq_unit.hh
| 6 +
src/cpu/o3/lsq_unit_impl.hh
| 12 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
| 7 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
| 12 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1251 ++++-----
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
| 2 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
| 3 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
| 1036 +--------
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
| 696 ++--
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
| 5 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 696 ++--
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
| 5 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
| 20 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 788 +++---
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
| 3 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 740 ++--
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
| 3 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
| 11 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
| 621 ++--
23 files changed, 2475 insertions(+), 3481 deletions(-)
diffs (truncated from 7098 to 300 lines):
diff -r 669e93d79ed9 -r 35e77c938919 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Sun Jan 29 02:04:34 2012 -0800
+++ b/configs/example/ruby_fs.py Sun Jan 29 03:27:15 2012 -0800
@@ -79,6 +79,7 @@
execfile(os.path.join(config_root, "common", "Options.py"))
(options, args) = parser.parse_args()
+options.ruby = True
if args:
print "Error: script doesn't take any positional arguments"
@@ -94,17 +95,11 @@
else:
bm = [SysConfig()]
-#
-# currently ruby fs only works in simple timing mode because ruby does not
-# support atomic accesses by devices. Also ruby_fs currently assumes
-# that is running a checkpoints that were created by ALPHA_FS under atomic
-# mode. Since switch cpus are not defined in these checkpoints, we don't
-# fast forward with the atomic cpu and instead set the FutureClass to None.
-# Therefore the cpus resolve to the correct names and unserialize correctly.
-#
-class CPUClass(TimingSimpleCPU): pass
-test_mem_mode = 'timing'
-FutureClass = None
+# Check for timing mode because ruby does not support atomic accesses
+if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
+ print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
+ sys.exit(1)
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = options.clock
diff -r 669e93d79ed9 -r 35e77c938919 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Sun Jan 29 02:04:34 2012 -0800
+++ b/src/cpu/o3/O3CPU.py Sun Jan 29 03:27:15 2012 -0800
@@ -139,3 +139,5 @@
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
+ needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
+ "Enable TSO Memory model")
diff -r 669e93d79ed9 -r 35e77c938919 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh Sun Jan 29 02:04:34 2012 -0800
+++ b/src/cpu/o3/lsq_unit.hh Sun Jan 29 03:27:15 2012 -0800
@@ -452,6 +452,9 @@
/** Has the blocked load been handled. */
bool loadBlockedHandled;
+ /** Whether or not a store is in flight. */
+ bool storeInFlight;
+
/** The sequence number of the blocked load. */
InstSeqNum blockedLoadSeqNum;
@@ -465,6 +468,9 @@
/** The packet that is pending free cache ports. */
PacketPtr pendingPkt;
+ /** Flag for memory model. */
+ bool needsTSO;
+
// Will also need how many read/write ports the Dcache has. Or keep track
// of that in stage that is one level up, and only call executeLoad/Store
// the appropriate number of times.
diff -r 669e93d79ed9 -r 35e77c938919 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Sun Jan 29 02:04:34 2012 -0800
+++ b/src/cpu/o3/lsq_unit_impl.hh Sun Jan 29 03:27:15 2012 -0800
@@ -138,7 +138,7 @@
LSQUnit<Impl>::LSQUnit()
: loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
isStoreBlocked(false), isLoadBlocked(false),
- loadBlockedHandled(false), hasPendingPkt(false)
+ loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false)
{
}
@@ -182,6 +182,7 @@
memDepViolator = NULL;
blockedLoadSeqNum = 0;
+ needsTSO = params->needsTSO;
}
template<class Impl>
@@ -770,6 +771,7 @@
storeWBIdx != storeTail &&
storeQueue[storeWBIdx].inst &&
storeQueue[storeWBIdx].canWB &&
+ ((!needsTSO) || (!storeInFlight)) &&
usedPorts < cachePorts) {
if (isStoreBlocked || lsq->cacheBlocked()) {
@@ -1090,6 +1092,10 @@
#endif
}
+ if (needsTSO) {
+ storeInFlight = true;
+ }
+
incrStIdx(storeWBIdx);
}
@@ -1163,6 +1169,10 @@
storeQueue[store_idx].inst->setCompleted();
+ if (needsTSO) {
+ storeInFlight = false;
+ }
+
// Tell the checker we've completed this instruction. Some stores
// may get reported twice to the checker, but the checker can
// handle that case.
diff -r 669e93d79ed9 -r 35e77c938919
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini Sun Jan
29 02:04:34 2012 -0800
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini Sun Jan
29 03:27:15 2012 -0800
@@ -15,7 +15,7 @@
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@@ -122,6 +122,7 @@
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=true
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -1311,7 +1312,7 @@
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -1331,7 +1332,7 @@
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
diff -r 669e93d79ed9 -r 35e77c938919
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout Sun Jan
29 02:04:34 2012 -0800
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout Sun Jan
29 03:27:15 2012 -0800
@@ -1,13 +1,15 @@
+Redirecting stdout to
build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simout
+Redirecting stderr to
build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 08:29:15
-gem5 executing on zizzer
+gem5 compiled Jan 28 2012 16:24:13
+gem5 started Jan 28 2012 16:29:18
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86_FS/gem5.opt -d
build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re
tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at:
/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5161177988500 because m5_exit instruction encountered
+Exiting @ tick 5164643202500 because m5_exit instruction encountered
diff -r 669e93d79ed9 -r 35e77c938919
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt Sun Jan
29 02:04:34 2012 -0800
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt Sun Jan
29 03:27:15 2012 -0800
@@ -1,108 +1,108 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.161178 #
Number of seconds simulated
-sim_ticks 5161177988500 #
Number of ticks simulated
-final_tick 5161177988500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 5.164643 #
Number of seconds simulated
+sim_ticks 5164643202500 #
Number of ticks simulated
+final_tick 5164643202500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 290092 #
Simulator instruction rate (inst/s)
-host_tick_rate 1780684720 #
Simulator tick rate (ticks/s)
-host_mem_usage 364016 #
Number of bytes of host memory used
-host_seconds 2898.42 #
Real time elapsed on the host
-sim_insts 840808469 #
Number of instructions simulated
-system.physmem.bytes_read 16106624 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read 1233856 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written 12115136 #
Number of bytes written to this memory
-system.physmem.num_reads 251666 #
Number of read requests responded to by this memory
-system.physmem.num_writes 189299 #
Number of write requests responded to by this memory
+host_inst_rate 258156 #
Simulator instruction rate (inst/s)
+host_tick_rate 1586008699 #
Simulator tick rate (ticks/s)
+host_mem_usage 390600 #
Number of bytes of host memory used
+host_seconds 3256.38 #
Real time elapsed on the host
+sim_insts 840653382 #
Number of instructions simulated
+system.physmem.bytes_read 15885120 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read 1235904 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written 12075328 #
Number of bytes written to this memory
+system.physmem.num_reads 248205 #
Number of read requests responded to by this memory
+system.physmem.num_writes 188677 #
Number of write requests responded to by this memory
system.physmem.num_other 0 #
Number of other requests responded to by this memory
-system.physmem.bw_read 3120726 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 239065 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 2347359 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 5468085 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 169467 #
number of replacements
-system.l2c.tagsinuse 38339.786444 #
Cycle average of tags in use
-system.l2c.total_refs 3812924 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 204660 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 18.630529 #
Average number of references to valid blocks.
+system.physmem.bw_read 3075744 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 239301 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2338076 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5413820 #
Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 166524 #
number of replacements
+system.l2c.tagsinuse 37860.019471 #
Cycle average of tags in use
+system.l2c.total_refs 3791499 #
Total number of references to valid blocks.
+system.l2c.sampled_refs 201257 #
Sample count of references to valid blocks.
+system.l2c.avg_refs 18.839091 #
Average number of references to valid blocks.
system.l2c.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 11950.408174 #
Average occupied blocks per context
-system.l2c.occ_blocks::1 26389.378270 #
Average occupied blocks per context
-system.l2c.occ_percent::0 0.182349 #
Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.402670 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2335607 #
number of ReadReq hits
-system.l2c.ReadReq_hits::1 145488 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 2481095 #
number of ReadReq hits
-system.l2c.Writeback_hits::0 1594493 #
number of Writeback hits
-system.l2c.Writeback_hits::total 1594493 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::0 327 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 327 #
number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 150672 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 150672 #
number of ReadExReq hits
-system.l2c.demand_hits::0 2486279 #
number of demand (read+write) hits
-system.l2c.demand_hits::1 145488 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2631767 #
number of demand (read+write) hits
-system.l2c.overall_hits::0 2486279 #
number of overall hits
-system.l2c.overall_hits::1 145488 #
number of overall hits
-system.l2c.overall_hits::total 2631767 #
number of overall hits
-system.l2c.ReadReq_misses::0 66850 #
number of ReadReq misses
-system.l2c.ReadReq_misses::1 109 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 66959 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 3932 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3932 #
number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 142221 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 142221 #
number of ReadExReq misses
-system.l2c.demand_misses::0 209071 #
number of demand (read+write) misses
-system.l2c.demand_misses::1 109 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 209180 #
number of demand (read+write) misses
-system.l2c.overall_misses::0 209071 #
number of overall misses
-system.l2c.overall_misses::1 109 #
number of overall misses
-system.l2c.overall_misses::total 209180 #
number of overall misses
-system.l2c.ReadReq_miss_latency 3511861000 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 38996000 #
number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 7442399000 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 10954260000 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 10954260000 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2402457 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 145597 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2548054 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 1594493 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1594493 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 4259 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 4259 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 292893 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 292893 #
number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2695350 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::1 145597 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2840947 #
number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2695350 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::1 145597 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2840947 #
number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.027826 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.000749 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.028574 #
miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.923221 #
miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.485573 #
miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.077567 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.000749 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.078316 #
miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.077567 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.000749 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.078316 #
miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52533.448018 #
average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 32218908.256881
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 32271441.704899
# average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 9917.599186 #
average UpgradeReq miss latency
+system.l2c.occ_blocks::0 11072.402172 #
Average occupied blocks per context
+system.l2c.occ_blocks::1 26787.617299 #
Average occupied blocks per context
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