changeset bb10807da889 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bb10807da889
description:
Merge with head, hopefully the last time for this batch.
diffstat:
SConstruct | 21 +-
ext/libelf/SConscript | 2 +
src/SConscript | 5 +-
src/arch/alpha/tlb.cc | 4 +-
src/arch/alpha/tlb.hh | 2 +-
src/arch/arm/insts/static_inst.hh | 1 +
src/arch/arm/insts/vfp.hh | 3 +
src/arch/arm/isa.cc | 53 +-
src/arch/arm/isa/formats/m5ops.isa | 1 +
src/arch/arm/isa/insts/m5ops.isa | 20 +-
src/arch/arm/isa/insts/misc.isa | 8 +-
src/arch/arm/isa/templates/basic.isa | 2 +-
src/arch/arm/miscregs.cc | 2 +-
src/arch/arm/table_walker.cc | 25 +-
src/arch/arm/table_walker.hh | 5 +-
src/arch/arm/tlb.cc | 20 +-
src/arch/arm/tlb.hh | 9 +-
src/arch/arm/utility.cc | 5 +
src/arch/generic/memhelpers.hh | 4 +-
src/arch/mips/faults.cc | 2 +-
src/arch/mips/faults.hh | 2 +-
src/arch/x86/bios/acpi.hh | 8 +-
src/arch/x86/bios/intelmp.cc | 2 +-
src/arch/x86/bios/intelmp.hh | 24 +-
src/arch/x86/bios/smbios.hh | 6 +-
src/base/fast_alloc.cc | 4 -
src/base/output.hh | 14 +-
src/base/range_map.hh | 2 +-
src/base/remote_gdb.hh | 2 +-
src/base/stl_helpers.hh | 4 +-
src/cpu/BaseCPU.py | 6 +-
src/cpu/CheckerCPU.py | 2 +-
src/cpu/DummyChecker.py | 42 +
src/cpu/SConscript | 2 +
src/cpu/base.cc | 43 +-
src/cpu/base.hh | 10 +-
src/cpu/base_dyn_inst.hh | 84 +-
src/cpu/base_dyn_inst_impl.hh | 11 +-
src/cpu/checker/cpu.cc | 373 +++---
src/cpu/checker/cpu.hh | 128 +-
src/cpu/checker/cpu_impl.hh | 531 ++++++---
src/cpu/checker/thread_context.hh | 106 +-
src/cpu/dummy_checker_builder.cc | 97 +
src/cpu/func_unit.hh | 6 +-
src/cpu/inorder/cpu.cc | 12 +-
src/cpu/inorder/cpu.hh | 8 +-
src/cpu/inorder/resource.cc | 2 +-
src/cpu/inorder/resource.hh | 12 +-
src/cpu/inorder/resource_pool.cc | 2 +-
src/cpu/inorder/resource_pool.hh | 2 +-
src/cpu/inorder/resources/cache_unit.hh | 3 -
src/cpu/inorder/thread_context.cc | 4 +-
src/cpu/nativetrace.hh | 2 +-
src/cpu/o3/O3CPU.py | 10 +-
src/cpu/o3/O3Checker.py | 2 +-
src/cpu/o3/bpred_unit.hh | 2 +-
src/cpu/o3/checker_builder.cc | 31 +-
src/cpu/o3/commit.hh | 4 +-
src/cpu/o3/commit_impl.hh | 13 +-
src/cpu/o3/cpu.cc | 14 +-
src/cpu/o3/cpu.hh | 6 +-
src/cpu/o3/decode.hh | 2 +-
src/cpu/o3/decode_impl.hh | 4 +-
src/cpu/o3/dyn_inst_impl.hh | 8 +-
src/cpu/o3/fetch.hh | 2 +-
src/cpu/o3/fetch_impl.hh | 8 +-
src/cpu/o3/fu_pool.cc | 2 +-
src/cpu/o3/fu_pool.hh | 3 +-
src/cpu/o3/iew.hh | 5 +-
src/cpu/o3/iew_impl.hh | 16 +-
src/cpu/o3/inst_queue.hh | 4 +-
src/cpu/o3/inst_queue_impl.hh | 4 +-
src/cpu/o3/lsq.hh | 2 +-
src/cpu/o3/lsq_unit.hh | 2 +-
src/cpu/o3/lsq_unit_impl.hh | 14 +-
src/cpu/o3/mem_dep_unit.cc | 8 +-
src/cpu/o3/mem_dep_unit.hh | 2 +-
src/cpu/o3/rename.hh | 2 +-
src/cpu/o3/sat_counter.hh | 3 +-
src/cpu/o3/thread_context.hh | 21 +
src/cpu/o3/thread_context_impl.hh | 17 +-
src/cpu/quiesce_event.hh | 3 +-
src/cpu/sched_list.hh | 180 ---
src/cpu/simple/BaseSimpleCPU.py | 9 +
src/cpu/simple/atomic.cc | 6 +-
src/cpu/simple/atomic.hh | 4 +-
src/cpu/simple/base.cc | 25 +-
src/cpu/simple/base.hh | 27 +-
src/cpu/simple/timing.cc | 6 +-
src/cpu/simple/timing.hh | 4 +-
src/cpu/simple_thread.cc | 25 +-
src/cpu/simple_thread.hh | 37 +-
src/cpu/static_inst.hh | 2 +-
src/cpu/thread_context.hh | 29 +
src/cpu/thread_state.hh | 2 +-
src/dev/alpha/tsunami_cchip.cc | 1 -
src/dev/alpha/tsunami_io.cc | 6 +-
src/dev/arm/pl111.cc | 9 +-
src/dev/arm/pl111.hh | 4 +-
src/dev/copy_engine.cc | 1 -
src/dev/disk_image.cc | 6 +-
src/dev/disk_image.hh | 2 +-
src/dev/ide_ctrl.cc | 5 +-
src/dev/ns_gige.cc | 42 +-
src/dev/pciconfigall.cc | 2 -
src/dev/pcidev.cc | 4 +-
src/mem/bus.cc | 3 +-
src/mem/cache/base.cc | 9 +-
src/mem/cache/base.hh | 11 +-
src/mem/cache/cache_impl.hh | 2 -
src/mem/cache/tags/iic.cc | 2 +-
src/mem/cache/tags/iic_repl/gen.cc | 2 +-
src/mem/cache/tags/iic_repl/gen.hh | 2 +-
src/mem/cache/tags/iic_repl/repl.hh | 2 +-
src/mem/packet.hh | 2 +-
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc | 11 +-
src/mem/ruby/system/Sequencer.hh | 2 +-
src/python/m5/SimObject.py | 2 +-
src/sim/core.hh | 2 +-
src/sim/process.cc | 4 +-
src/sim/process.hh | 4 +-
src/sim/process_impl.hh | 2 +-
src/sim/pseudo_inst.cc | 45 +-
src/sim/pseudo_inst.hh | 2 +
src/sim/serialize.cc | 7 +-
src/sim/sim_object.cc | 2 +-
src/sim/sim_object.hh | 3 +-
src/sim/syscall_emul.hh | 56 +-
util/m5/m5.c | 43 +-
util/m5/m5op.h | 1 +
util/m5/m5op_arm.S | 2 +
util/m5/m5ops.h | 1 +
132 files changed, 1718 insertions(+), 908 deletions(-)
diffs (truncated from 5645 to 300 lines):
diff -r 8af87554ad7e -r bb10807da889 SConstruct
--- a/SConstruct Mon Jan 30 21:07:57 2012 -0800
+++ b/SConstruct Tue Jan 31 22:40:08 2012 -0800
@@ -473,7 +473,8 @@
main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
main['SUNCC'] = CXX_V and CXX_V.find('Sun C++') >= 0
main['ICC'] = CXX_V and CXX_V.find('Intel') >= 0
-if main['GCC'] + main['SUNCC'] + main['ICC'] > 1:
+main['CLANG'] = CXX_V and CXX_V.find('clang') >= 0
+if main['GCC'] + main['SUNCC'] + main['ICC'] + main['CLANG'] > 1:
print 'Error: How can we have two at the same time?'
Exit(1)
@@ -501,6 +502,24 @@
main.Append(CCFLAGS=['-library=stlport4'])
main.Append(CCFLAGS=['-xar'])
#main.Append(CCFLAGS=['-instances=semiexplicit'])
+elif main['CLANG']:
+ clang_version_re = re.compile(".* version (\d+\.\d+)")
+ clang_version_match = clang_version_re.match(CXX_version)
+ if (clang_version_match):
+ clang_version = clang_version_match.groups()[0]
+ if compareVersions(clang_version, "2.9") < 0:
+ print 'Error: clang version 2.9 or newer required.'
+ print ' Installed version:', clang_version
+ Exit(1)
+ else:
+ print 'Error: Unable to determine clang version.'
+ Exit(1)
+
+ main.Append(CCFLAGS=['-pipe'])
+ main.Append(CCFLAGS=['-fno-strict-aliasing'])
+ main.Append(CCFLAGS=['-Wall', '-Wno-sign-compare', '-Wundef'])
+ main.Append(CCFLAGS=['-Wno-tautological-compare'])
+ main.Append(CCFLAGS=['-Wno-self-assign'])
else:
print 'Error: Don\'t know what compiler options to use for your compiler.'
print ' Please fix SConstruct and src/SConscript and try again.'
diff -r 8af87554ad7e -r bb10807da889 ext/libelf/SConscript
--- a/ext/libelf/SConscript Mon Jan 30 21:07:57 2012 -0800
+++ b/ext/libelf/SConscript Tue Jan 31 22:40:08 2012 -0800
@@ -94,6 +94,8 @@
major,minor,dot = [int(x) for x in m4env['GCC_VERSION'].split('.')]
if major >= 4:
m4env.Append(CCFLAGS=['-Wno-pointer-sign'])
+if m4env['CLANG']:
+ m4env.Append(CCFLAGS=['-Wno-initializer-overrides', '-Wno-pointer-sign'])
m4env.Append(CCFLAGS=['-Wno-implicit'])
del m4env['CPPPATH']
diff -r 8af87554ad7e -r bb10807da889 src/SConscript
--- a/src/SConscript Mon Jan 30 21:07:57 2012 -0800
+++ b/src/SConscript Tue Jan 31 22:40:08 2012 -0800
@@ -854,6 +854,9 @@
swig_env.Append(CCFLAGS='-Wno-unused-label')
if compareVersions(env['GCC_VERSION'], '4.6.0') != -1:
swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
+ if env['CLANG']:
+ swig_env.Append(CCFLAGS=['-Wno-unused-label'])
+
werror_env = new_env.Clone()
werror_env.Append(CCFLAGS='-Werror')
@@ -928,7 +931,7 @@
# Debug binary
ccflags = {}
-if env['GCC']:
+if env['GCC'] or env['CLANG']:
if sys.platform == 'sunos5':
ccflags['debug'] = '-gstabs+'
else:
diff -r 8af87554ad7e -r bb10807da889 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Mon Jan 30 21:07:57 2012 -0800
+++ b/src/arch/alpha/tlb.cc Tue Jan 31 22:40:08 2012 -0800
@@ -64,7 +64,7 @@
: BaseTLB(p), size(p->size), nlu(0)
{
table = new TlbEntry[size];
- memset(table, 0, sizeof(TlbEntry[size]));
+ memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
}
@@ -280,7 +280,7 @@
TLB::flushAll()
{
DPRINTF(TLB, "flushAll\n");
- memset(table, 0, sizeof(TlbEntry[size]));
+ memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
lookupTable.clear();
nlu = 0;
diff -r 8af87554ad7e -r bb10807da889 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Mon Jan 30 21:07:57 2012 -0800
+++ b/src/arch/alpha/tlb.hh Tue Jan 31 22:40:08 2012 -0800
@@ -49,7 +49,7 @@
namespace AlphaISA {
-class TlbEntry;
+struct TlbEntry;
class TLB : public BaseTLB
{
diff -r 8af87554ad7e -r bb10807da889 src/arch/arm/insts/static_inst.hh
--- a/src/arch/arm/insts/static_inst.hh Mon Jan 30 21:07:57 2012 -0800
+++ b/src/arch/arm/insts/static_inst.hh Tue Jan 31 22:40:08 2012 -0800
@@ -46,6 +46,7 @@
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "sim/byteswap.hh"
#include "sim/full_system.hh"
namespace ArmISA
diff -r 8af87554ad7e -r bb10807da889 src/arch/arm/insts/vfp.hh
--- a/src/arch/arm/insts/vfp.hh Mon Jan 30 21:07:57 2012 -0800
+++ b/src/arch/arm/insts/vfp.hh Tue Jan 31 22:40:08 2012 -0800
@@ -107,6 +107,9 @@
VfpRoundZero = 3
};
+static inline float bitsToFp(uint64_t, float);
+static inline uint32_t fpToBits(float);
+
template <class fpType>
static inline bool
flushToZero(fpType &op)
diff -r 8af87554ad7e -r bb10807da889 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Jan 30 21:07:57 2012 -0800
+++ b/src/arch/arm/isa.cc Tue Jan 31 22:40:08 2012 -0800
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -39,12 +39,17 @@
*/
#include "arch/arm/isa.hh"
+#include "config/use_checker.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
namespace ArmISA
{
@@ -279,7 +284,11 @@
PCState pc = tc->pcState();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
+#if USE_CHECKER
+ tc->pcStateNoRecord(pc);
+#else
tc->pcState(pc);
+#endif //USE_CHECKER
} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
misc_reg < MISCREG_CP15_END) {
panic("Unimplemented CP15 register %s wrote with %#x.\n",
@@ -382,6 +391,14 @@
oc = sys->getThreadContext(x);
oc->getDTBPtr()->allCpusCaching();
oc->getITBPtr()->allCpusCaching();
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getDTBPtr()->allCpusCaching();
+ checker->getITBPtr()->allCpusCaching();
+ }
+#endif
}
return;
}
@@ -399,6 +416,14 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAll();
oc->getDTBPtr()->flushAll();
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushAll();
+ checker->getDTBPtr()->flushAll();
+ }
+#endif
}
return;
case MISCREG_ITLBIALL:
@@ -417,6 +442,16 @@
bits(newVal, 7,0));
oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ }
+#endif
}
return;
case MISCREG_TLBIASIDIS:
@@ -427,6 +462,14 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
+ checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+ }
+#endif
}
return;
case MISCREG_TLBIMVAAIS:
@@ -437,6 +480,14 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
+ checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+ }
+#endif
}
return;
case MISCREG_ITLBIMVA:
diff -r 8af87554ad7e -r bb10807da889 src/arch/arm/isa/formats/m5ops.isa
--- a/src/arch/arm/isa/formats/m5ops.isa Mon Jan 30 21:07:57 2012 -0800
+++ b/src/arch/arm/isa/formats/m5ops.isa Tue Jan 31 22:40:08 2012 -0800
@@ -59,6 +59,7 @@
case 0x41: return new Dumpstats(machInst);
case 0x42: return new Dumpresetstats(machInst);
case 0x43: return new M5checkpoint(machInst);
+ case 0x4F: return new M5writefile(machInst);
case 0x50: return new M5readfile(machInst);
case 0x51: return new M5break(machInst);
case 0x52: return new M5switchcpu(machInst);
diff -r 8af87554ad7e -r bb10807da889 src/arch/arm/isa/insts/m5ops.isa
--- a/src/arch/arm/isa/insts/m5ops.isa Mon Jan 30 21:07:57 2012 -0800
+++ b/src/arch/arm/isa/insts/m5ops.isa Tue Jan 31 22:40:08 2012 -0800
@@ -243,7 +243,7 @@
m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
{ "code": m5checkpoint_code,
"predicate_test": predicateTest },
- ["IsNonSpeculative"])
+ ["IsNonSpeculative", "IsUnverifiable"])
header_output += BasicDeclare.subst(m5checkpointIop)
decoder_output += BasicConstructor.subst(m5checkpointIop)
exec_output += PredOpExecute.subst(m5checkpointIop)
@@ -256,11 +256,27 @@
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
{ "code": m5readfileCode,
"predicate_test": predicateTest },
- ["IsNonSpeculative"])
+ ["IsNonSpeculative", "IsUnverifiable"])
header_output += BasicDeclare.subst(m5readfileIop)
decoder_output += BasicConstructor.subst(m5readfileIop)
exec_output += PredOpExecute.subst(m5readfileIop)
+ m5writefileCode = '''
+ int n = 4;
+ uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
+ n = 6;
+ Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false);
+ R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset,
+ filenameAddr);
+ '''
+ m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp",
+ { "code": m5writefileCode,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative"])
+ header_output += BasicDeclare.subst(m5writefileIop)
+ decoder_output += BasicConstructor.subst(m5writefileIop)
+ exec_output += PredOpExecute.subst(m5writefileIop)
+
m5breakIop = InstObjParams("m5break", "M5break", "PredOp",
{ "code": "PseudoInst::debugbreak(xc->tcBase());",
"predicate_test": predicateTest },
diff -r 8af87554ad7e -r bb10807da889 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Mon Jan 30 21:07:57 2012 -0800
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