Its one patch. The actual amount of code related to the SE/FS code
amounted to two or three additions of "if (FullSystem) {}". The bulk of
this patch in the C++ code goes through and removes #ifdef
USE_CHECKER/#endif pairs. In the SCons files I was removing "if
buildEnv['USE_CHECKER]:" lines. The changes that really need looking at
exist in O3CPU.py, BaseCPU.py, fs.py and se.py.
Geoff
On Wed, Feb 8, 2012 at 1:52 PM, Gabe Black <[email protected]> wrote:
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1031/
>
> Is this one commit or two squished together? If it's only one, I'm afraid the
> meaningful changes will get lost in the merge noise, especially since people
> (or at least I) don't expect merges to do anything other than merge.
>
>
> - Gabe
>
> On February 8th, 2012, 7:45 a.m., Geoffrey Blake wrote:
> Review request for Default.
> By Geoffrey Blake.
>
> *Updated Feb. 8, 2012, 7:45 a.m.*
> Description
>
> CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
>
> Enables the CheckerCPU to be enabled at runtime with the --checker option
> from the configs/example/fs.py and configs/example/se.py configuration
> files. Also merges with the SE/FS changes.
>
> Testing
>
> Compiles with ARM ISA.
> Boots linux with O3 model attached to Checker in FS mode.
> Runs simple HelloWorld in SE mode.
>
> Diffs
>
> - SConstruct (8f354c5a1634)
> - configs/common/Options.py (8f354c5a1634)
> - configs/common/Simulation.py (8f354c5a1634)
> - configs/example/fs.py (8f354c5a1634)
> - configs/example/se.py (8f354c5a1634)
> - src/arch/SConscript (8f354c5a1634)
> - src/arch/arm/isa.cc (8f354c5a1634)
> - src/arch/arm/utility.cc (8f354c5a1634)
> - src/cpu/BaseCPU.py (8f354c5a1634)
> - src/cpu/SConscript (8f354c5a1634)
> - src/cpu/base.cc (8f354c5a1634)
> - src/cpu/base_dyn_inst.hh (8f354c5a1634)
> - src/cpu/base_dyn_inst_impl.hh (8f354c5a1634)
> - src/cpu/checker/cpu.cc (8f354c5a1634)
> - src/cpu/checker/cpu_impl.hh (8f354c5a1634)
> - src/cpu/checker/thread_context.hh (8f354c5a1634)
> - src/cpu/o3/O3CPU.py (8f354c5a1634)
> - src/cpu/o3/SConscript (8f354c5a1634)
> - src/cpu/o3/commit_impl.hh (8f354c5a1634)
> - src/cpu/o3/cpu.hh (8f354c5a1634)
> - src/cpu/o3/cpu.cc (8f354c5a1634)
> - src/cpu/o3/cpu_builder.cc (8f354c5a1634)
> - src/cpu/o3/dyn_inst_impl.hh (8f354c5a1634)
> - src/cpu/o3/fetch_impl.hh (8f354c5a1634)
> - src/cpu/o3/iew_impl.hh (8f354c5a1634)
> - src/cpu/o3/lsq_unit_impl.hh (8f354c5a1634)
> - src/cpu/o3/thread_context.hh (8f354c5a1634)
> - src/cpu/o3/thread_context_impl.hh (8f354c5a1634)
> - src/cpu/ozone/OzoneCPU.py (8f354c5a1634)
> - src/cpu/ozone/SConscript (8f354c5a1634)
> - src/cpu/ozone/cpu_impl.hh (8f354c5a1634)
> - src/cpu/ozone/front_end_impl.hh (8f354c5a1634)
> - src/cpu/ozone/lw_back_end_impl.hh (8f354c5a1634)
> - src/cpu/ozone/lw_lsq_impl.hh (8f354c5a1634)
> - src/cpu/simple/BaseSimpleCPU.py (8f354c5a1634)
> - src/cpu/simple/base.hh (8f354c5a1634)
> - src/cpu/simple/base.cc (8f354c5a1634)
> - src/cpu/simple_thread.hh (8f354c5a1634)
> - src/cpu/thread_context.hh (8f354c5a1634)
>
> View Diff <http://reviews.gem5.org/r/1031/diff/>
>
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