> On Feb. 9, 2012, 1:55 a.m., Gabe Black wrote: > > src/cpu/checker/cpu_impl.hh, line 402 > > <http://reviews.gem5.org/r/1031/diff/1/?file=23033#file23033line402> > > > > Why does this need to be FullSystem only? > > Geoffrey Blake wrote: > Yes. In SE mode faults just happen and no PC change occurs right? Only > in FS will the PC be vectored to a fault handler. > > Gabe Black wrote: > No. In SE faults *usually* just happen (typically panicing or updating > the TLB), but that's not a hard rule. In SPARC specifically there are faults > that do register window spills and fills in SE mode in actual handlers > injected into memory before the process starts.
That's a good bit of info to know if someone wants to use the Checker with the SPARC ISA. But since I'm only worried about it working with ARM for now I'll put this off to the side right now. > On Feb. 9, 2012, 1:55 a.m., Gabe Black wrote: > > src/arch/arm/isa.cc, line 291 > > <http://reviews.gem5.org/r/1031/diff/1/?file=23025#file23025line291> > > > > Is the dynamic_cast necessary? What type does getCheckerCpuPtr return? > > If you remove it here, remove it later on too. > > Geoffrey Blake wrote: > It returns a pointer to the BaseCPU type. The dynamic_cast is technically > necessary. > > Gabe Black wrote: > The dynamic_cast is basically necessary *if* it returns a BaseCPU > pointer. Why does it do that instead of returning a CheckerCPU pointer? Is > CheckerCPU really an O3 thing and not a generic class? If it's generic it > makes sense to return it directly. If not, maybe something like O3CheckerCPU > would be a better name, although renaming it is outside the scope of your > change. The CheckerCPU is a derived type from the BaseCPU class. getCheckerCpuPtr() calls the Checker's SimpleThread context with getCpuPtr() which returns a BaseCPU ptr to the checker. At some point the cast is needed. I'll make a patch to hide the casts inside the Checker code to make it more explicit what is going on. - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1031/#review2098 ----------------------------------------------------------- On Feb. 10, 2012, 3:24 p.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1031/ > ----------------------------------------------------------- > > (Updated Feb. 10, 2012, 3:24 p.m.) > > > Review request for Default. > > > Description > ------- > > CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable > > Enables the CheckerCPU to be enabled at runtime with the --checker option > from the configs/example/fs.py and configs/example/se.py configuration > files. Also merges with the SE/FS changes. > > > Diffs > ----- > > SConstruct 8f354c5a1634 > configs/common/Options.py 8f354c5a1634 > configs/common/Simulation.py 8f354c5a1634 > configs/example/fs.py 8f354c5a1634 > configs/example/se.py 8f354c5a1634 > src/arch/SConscript 8f354c5a1634 > src/arch/arm/isa.cc 8f354c5a1634 > src/arch/arm/utility.cc 8f354c5a1634 > src/cpu/BaseCPU.py 8f354c5a1634 > src/cpu/SConscript 8f354c5a1634 > src/cpu/base.cc 8f354c5a1634 > src/cpu/base_dyn_inst.hh 8f354c5a1634 > src/cpu/base_dyn_inst_impl.hh 8f354c5a1634 > src/cpu/checker/cpu.cc 8f354c5a1634 > src/cpu/checker/cpu_impl.hh 8f354c5a1634 > src/cpu/checker/thread_context.hh 8f354c5a1634 > src/cpu/o3/O3CPU.py 8f354c5a1634 > src/cpu/o3/SConscript 8f354c5a1634 > src/cpu/o3/commit_impl.hh 8f354c5a1634 > src/cpu/o3/cpu.hh 8f354c5a1634 > src/cpu/o3/cpu.cc 8f354c5a1634 > src/cpu/o3/cpu_builder.cc 8f354c5a1634 > src/cpu/o3/dyn_inst_impl.hh 8f354c5a1634 > src/cpu/o3/fetch_impl.hh 8f354c5a1634 > src/cpu/o3/iew_impl.hh 8f354c5a1634 > src/cpu/o3/lsq_unit_impl.hh 8f354c5a1634 > src/cpu/o3/thread_context.hh 8f354c5a1634 > src/cpu/o3/thread_context_impl.hh 8f354c5a1634 > src/cpu/ozone/OzoneCPU.py 8f354c5a1634 > src/cpu/ozone/SConscript 8f354c5a1634 > src/cpu/ozone/cpu_impl.hh 8f354c5a1634 > src/cpu/ozone/front_end_impl.hh 8f354c5a1634 > src/cpu/ozone/lw_back_end_impl.hh 8f354c5a1634 > src/cpu/ozone/lw_lsq_impl.hh 8f354c5a1634 > src/cpu/simple/BaseSimpleCPU.py 8f354c5a1634 > src/cpu/simple/base.hh 8f354c5a1634 > src/cpu/simple/base.cc 8f354c5a1634 > src/cpu/simple_thread.hh 8f354c5a1634 > src/cpu/thread_context.hh 8f354c5a1634 > > Diff: http://reviews.gem5.org/r/1031/diff/diff > > > Testing > ------- > > Compiles with ARM ISA. > Boots linux with O3 model attached to Checker in FS mode. > Runs simple HelloWorld in SE mode. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
